3 This file is part of the ARM-Crypto-Lib.
4 Copyright (C) 2010 Daniel Otte (daniel.otte@rub.de)
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "hw_uart_regs.h"
23 #include "uart_defines.h"
26 void calc_baud_values(uint32_t baudrate, uint16_t* intdivider, uint8_t* fracdivider, uint8_t* highspeed){
32 uart_freq = sysclk_get_freq();
33 *highspeed = ((baudrate*16L)>uart_freq)?1:0;
34 // tmp = (((uint64_t)UART_FREQ)*128LL)/(((*highspeed)?8L:16L)*baudrate);
35 tmp = uart_freq<<((*highspeed)?(7-3):(7-4));
39 *fracdivider = (uint8_t)(tmp&0x3f);
40 *intdivider = (uint16_t)(tmp>>6);
44 uint32_t uart_base[] = { UART0_BASE, UART1_BASE, UART2_BASE };
47 uint32_t gpio_base[] =
48 { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE,
49 GPIOE_BASE, GPIOF_BASE, GPIOG_BASE, GPIOH_BASE,
54 uint8_t uart_tx_gpio[] = { GPIOA, GPIOD, GPIOG };
56 uint8_t uart_rx_gpio[] = { GPIOA, GPIOD, GPIOG };
58 uint8_t uart_tx_pin[] = { 1, 1, 1 };
60 uint8_t uart_rx_pin[] = { 0, 0, 0 };
62 uint8_t uart_tx_pctl[] = {1, 5, 1};
64 uint8_t uart_rx_pctl[] = {1, 5, 1};
66 uint8_t uart_init(uint8_t uartno, uint32_t baudrate, uint8_t databits, uint8_t paraty, uint8_t stopbits){
72 return UART_ERROR_WRONG_UART;
74 if(databits>UART_DATABITS_8){
75 return UART_ERROR_WRONG_DATABITS;
77 if(paraty>UART_PARATY_SPACE){
78 return UART_ERROR_WRONG_PARATY;
80 if(stopbits>UART_STOPBITS_TWO){
81 return UART_ERROR_WRONG_STOPBITS;
83 /* enable clock for uart */
84 HW_REG(SYSCTL_BASE+RCGC1_OFFSET) |= _BV(uartno);
85 /* enable clock for gpio*/
86 HW_REG(SYSCTL_BASE+RCGC2_OFFSET) |= _BV(uart_rx_gpio[uartno]) | _BV(uart_tx_gpio[uartno]);
87 HW_REG(SYSCTL_BASE+RCGC2_OFFSET) |= 1;
89 HW_REG(gpio_base[uart_rx_gpio[uartno]] + GPIO_ODR_OFFSET) &= ~_BV(uart_rx_pin[uartno]); /* open drain */
90 HW_REG(gpio_base[uart_tx_gpio[uartno]] + GPIO_ODR_OFFSET) &= ~_BV(uart_tx_pin[uartno]); /* open drain */
91 HW_REG(gpio_base[uart_rx_gpio[uartno]] + GPIO_PUR_OFFSET) &= ~_BV(uart_rx_pin[uartno]); /* pull-up */
92 HW_REG(gpio_base[uart_tx_gpio[uartno]] + GPIO_PUR_OFFSET) &= ~_BV(uart_tx_pin[uartno]); /* pull-up */
93 HW_REG(gpio_base[uart_rx_gpio[uartno]] + GPIO_PDR_OFFSET) &= ~_BV(uart_rx_pin[uartno]); /* pull-down*/
94 HW_REG(gpio_base[uart_tx_gpio[uartno]] + GPIO_PDR_OFFSET) &= ~_BV(uart_tx_pin[uartno]); /* pull-down*/
95 HW_REG(gpio_base[uart_rx_gpio[uartno]] + GPIO_DEN_OFFSET) |= _BV(uart_rx_pin[uartno]); /* digital enable */
96 HW_REG(gpio_base[uart_tx_gpio[uartno]] + GPIO_DEN_OFFSET) |= _BV(uart_tx_pin[uartno]); /* digital enable */
98 /* switch to alternate function for rx */
99 HW_REG(gpio_base[uart_rx_gpio[uartno]]+GPIO_AFSEL_OFFSET) |= _BV(uart_rx_pin[uartno]);
100 /* switch to alternate function for tx */
101 HW_REG(gpio_base[uart_tx_gpio[uartno]]+GPIO_AFSEL_OFFSET) |= _BV(uart_tx_pin[uartno]);
102 /* switch multiplexer to uart for rx */
103 HW_REG(gpio_base[uart_rx_gpio[uartno]]+GPIO_PCTL_OFFSET) &= ~(0x0f<<(uart_rx_pin[uartno]*4));
104 HW_REG(gpio_base[uart_rx_gpio[uartno]]+GPIO_PCTL_OFFSET) |= ((uart_rx_pctl[uartno])<<(uart_rx_pin[uartno]*4));
105 /* switch multiplexer to uart for tx */
106 HW_REG(gpio_base[uart_tx_gpio[uartno]]+GPIO_PCTL_OFFSET) &= ~(0x0f<<(uart_tx_pin[uartno]*4));
107 HW_REG(gpio_base[uart_tx_gpio[uartno]]+GPIO_PCTL_OFFSET) |= ((uart_tx_pctl[uartno])<<(uart_tx_pin[uartno]*4));
108 /* set pins to be 2mA */
109 HW_REG(gpio_base[uart_rx_gpio[uartno]]+GPIO_DR2R_OFFSET) |= _BV(uart_rx_pin[uartno]);
110 HW_REG(gpio_base[uart_tx_gpio[uartno]]+GPIO_DR2R_OFFSET) |= _BV(uart_tx_pin[uartno]);
111 /* configure rx pin as input */
112 HW_REG(gpio_base[uart_rx_gpio[uartno]]+GPIO_DIR_OFFSET) &= ~_BV(uart_rx_pin[uartno]);
113 /* configure tx pin as output */
114 HW_REG(gpio_base[uart_tx_gpio[uartno]]+GPIO_DIR_OFFSET) |= _BV(uart_tx_pin[uartno]);
117 HW_REG(uart_base[uartno]+UARTCTL_OFFSET) &= ~_BV(UART_UARTEN);
118 /* set baudrate parameters */
122 calc_baud_values(baudrate, &ibrd, &fbrd, &highspeed);
123 tmp=HW_REG(uart_base[uartno]+UARTLCRH_OFFSET);
124 HW16_REG(uart_base[uartno]+UARTIBRD_OFFSET) = ibrd;
125 HW8_REG(uart_base[uartno]+UARTFBRD_OFFSET) = fbrd;
126 HW_REG(uart_base[uartno]+UARTLCRH_OFFSET) = tmp;
127 /* wait until uart is no longer busy */
128 while(HW_REG(uart_base[uartno]+UARTFR_OFFSET)&_BV(UART_BUSY))
131 HW_REG(uart_base[uartno]+UARTLCRH_OFFSET) &= ~_BV(UART_FEN);
132 /* set line parameters (bits, paraty, stopbits*/
133 tmp = HW_REG(uart_base[uartno]+UARTLCRH_OFFSET);
135 tmp |= (paraty==UART_PARATY_MARK||paraty==UART_PARATY_SPACE)?_BV(7):0; /* set flag for mark or space paraty*/
137 tmp |= _BV(UART_FEN); /* enable FIFOs */
138 tmp |= (stopbits==UART_STOPBITS_TWO)?_BV(3):0;
139 tmp |= (paraty==UART_PARATY_EVEN || paraty==UART_PARATY_MARK)?_BV(2):0;
140 tmp |= (paraty!=UART_PARATY_NONE)?_BV(1):0;
141 HW_REG(uart_base[uartno]+UARTLCRH_OFFSET) = tmp;
142 /* set the highspeed bit accordingly */
144 HW_REG(uart_base[uartno]+UARTCTL_OFFSET) |= _BV(UART_HSE);
146 HW_REG(uart_base[uartno]+UARTCTL_OFFSET) &= ~_BV(UART_HSE);
148 HW_REG(uart_base[uartno]+UARTFR_OFFSET) = 0;
149 HW_REG(uart_base[uartno]+UARTCTL_OFFSET) |= _BV(UART_RXE) | _BV(UART_TXE);
150 HW_REG(uart_base[uartno]+UARTCTL_OFFSET) |= _BV(UART_UARTEN);
152 return UART_ERROR_OK;
156 void uart_putc(uint8_t uartno, uint8_t byte){
160 /* wait while the FIFO is full */
161 while(HW_REG(uart_base[uartno]+UARTFR_OFFSET)&_BV(UART_TXFF))
163 HW_REG(uart_base[uartno]+UARTDR_OFFSET) = (uint32_t)byte;
166 uint16_t uart_getc(uint8_t uartno){
170 /* wait while the FIFO is empty */
171 while(HW_REG(uart_base[uartno]+UARTFR_OFFSET)&_BV(UART_RXFE))
173 return (uint16_t)HW_REG(uart_base[uartno]+UARTDR_OFFSET);
176 uint32_t uart_dataavail(uint8_t uartno){
180 /* wait while the FIFO is empty */
181 return(HW_REG(uart_base[uartno]+UARTFR_OFFSET)&_BV(UART_RXFE))?0:1;
184 void uart_flush(uint8_t uartno){
188 while((HW_REG(uart_base[uartno]+UARTCTL_OFFSET)&_BV(UART_EOT)) == 0)