3 This file is part of the AVR-Crypto-Lib.
4 Copyright (C) 2010 Daniel Otte (daniel.otte@rub.de)
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define SET_REG(r,v) (*((volatile uint32_t*)(r))) = (v)
26 #define GET_REG(r) (*((volatile uint32_t*)(r)))
27 #define HW_REG(r) (*((volatile uint32_t*)(r)))
28 #define HW16_REG(r) (*((volatile uint16_t*)(r)))
29 #define HW8_REG(r) (*((volatile uint8_t*)(r)))
30 #define _BV(x) (1UL<<(x))
32 #define SYSCTL_BASE 0x400FE000
33 #define DID0_OFFSET 0x000
34 #define DID1_OFFSET 0x004
35 #define DC0_OFFSET 0x008
36 #define DC1_OFFSET 0x010
37 #define DC2_OFFSET 0x014
38 #define DC3_OFFSET 0x018
39 #define DC4_OFFSET 0x01C
40 #define DC5_OFFSET 0x020
41 #define DC6_OFFSET 0x024
42 #define DC7_OFFSET 0x028
43 #define DC8_OFFSET 0x02C
44 #define PBORCTL_OFFSET 0x030
45 #define SRCR0_OFFSET 0x040
46 #define SRCR1_OFFSET 0x044
47 #define SRCR2_OFFSET 0x048
48 #define RIS_OFFSET 0x050
49 #define IMC_OFFSET 0x054
50 #define MISC_OFFSET 0x058
51 #define RESC_OFFSET 0x05C
52 #define RCC_OFFSET 0x060
53 #define PLLCFG_OFFSET 0x064
54 #define GPIOHBCTL_OFFSET 0x06C
55 #define RCC2_OFFSET 0x070
56 #define MOSCCTL_OFFSET 0x07C
57 #define RCGC0_OFFSET 0x100
58 #define RCGC1_OFFSET 0x104
59 #define RCGC2_OFFSET 0x108
60 #define SCGC0_OFFSET 0x110
61 #define SCGC1_OFFSET 0x114
62 #define SCGC2_OFFSET 0x118
63 #define DCGC0_OFFSET 0x120
64 #define DCGC1_OFFSET 0x124
65 #define DCGC2_OFFSET 0x128
66 #define DSLPCLKCFG_OFFSET 0x144
67 #define PIOSCCAL_OFFSET 0x150
68 #define PIOSCSTAT_OFFSET 0x154
69 #define I2SMCLKCFG_OFFSET 0x170
70 #define DC9_OFFSET 0x190
71 #define NVMSTAT_OFFSET 0x1A0
75 #define RCC_USESYSDIV 22
83 #define RCC2_USERCC2 31
84 #define RCC2_DIV400 30
85 #define RCC2_SYSDIV2 23
86 #define RCC2_SYSDIV2LSB 22
87 #define RCC2_USBPWRDN 14
88 #define RCC2_PWRDN2 13
89 #define RCC2_BYPASS2 11
94 #define RCGC0_MAXADC0SPD 8
95 #define RCGC0_MAXADC1SPD 10
100 #define RCGC0_WDT1 28
102 #define RCGC1_UART0 0
103 #define RCGC1_UART1 1
104 #define RCGC1_UART2 2
107 #define RCGC1_I2C0 12
108 #define RCGC1_I2C1 14
109 #define RCGC1_TIMER0 16
110 #define RCGC1_TIMER1 17
111 #define RCGC1_TIMER2 18
112 #define RCGC1_TIMER3 19
113 #define RCGC1_COMP0 24
114 #define RCGC1_COMP1 25
115 #define RCGC1_COMP2 26
116 #define RCGC1_I2S0 28
117 #define RCGC1_EPI0 30
119 #define RCGC2_GPIOA 0
120 #define RCGC2_GPIOB 1
121 #define RCGC2_GPIOC 2
122 #define RCGC2_GPIOD 3
123 #define RCGC2_GPIOE 4
124 #define RCGC2_GPIOF 5
125 #define RCGC2_GPIOG 6
126 #define RCGC2_GPIOH 7
127 #define RCGC2_GPIOJ 8
128 #define RCGC2_UDMA 13
129 #define RCGC2_USB0 16
130 #define RCGC2_EMAC0 28
131 #define RCGC2_EPHY0 30
134 #define RIS_MOSCPUPRIS 8
135 #define RIS_USBPLLLRIS 7
136 #define RIS_PLLLRIS 6
149 #define GPIOA_BASE 0x40004000
150 #define GPIOB_BASE 0x40005000
151 #define GPIOC_BASE 0x40006000
152 #define GPIOD_BASE 0x40007000
153 #define GPIOE_BASE 0x40024000
154 #define GPIOF_BASE 0x40025000
155 #define GPIOG_BASE 0x40026000
156 #define GPIOH_BASE 0x40027000
157 #define GPIOJ_BASE 0x4003D000
159 #define GPIO_DATA_OFFSET 0x000
160 #define GPIO_DIR_OFFSET 0x400
161 #define GPIO_IS_OFFSET 0x404
162 #define GPIO_IBE_OFFSET 0x408
163 #define GPIO_IEV_OFFSET 0x40C
164 #define GPIO_IM_OFFSET 0x410
165 #define GPIO_RIS_OFFSET 0x414
166 #define GPIO_MIS_OFFSET 0x418
167 #define GPIO_ICR_OFFSET 0x41C
168 #define GPIO_AFSEL_OFFSET 0x420
169 #define GPIO_DR2R_OFFSET 0x500
170 #define GPIO_DR4R_OFFSET 0x504
171 #define GPIO_DR8R_OFFSET 0x508
172 #define GPIO_ODR_OFFSET 0x50C
173 #define GPIO_PUR_OFFSET 0x510
174 #define GPIO_PDR_OFFSET 0x514
175 #define GPIO_SLR_OFFSET 0x518
176 #define GPIO_DEN_OFFSET 0x51C
177 #define GPIO_LOCK_OFFSET 0x520
178 #define GPIO_CR_OFFSET 0x524
179 #define GPIO_AMSEL_OFFSET 0x528
180 #define GPIO_PCTL_OFFSET 0x52C
181 #define GPIO_PeriphID4_OFFSET 0xFD0
182 #define GPIO_PeriphID5_OFFSET 0xFD4
183 #define GPIO_PeriphID6_OFFSET 0xFD8
184 #define GPIO_PeriphID7_OFFSET 0xFDC
185 #define GPIO_PeriphID0_OFFSET 0xFE0
186 #define GPIO_PeriphID1_OFFSET 0xFE4
187 #define GPIO_PeriphID2_OFFSET 0xFE8
188 #define GPIO_PeriphID3_OFFSET 0xFEC
189 #define GPIO_PCellID0_OFFSET 0xFF0
190 #define GPIO_PCellID1_OFFSET 0xFF4
191 #define GPIO_PCellID2_OFFSET 0xFF8
192 #define GPIO_PCellID3_OFFSET 0xFFC
195 #define ISR_ENABLE_VECTOR 0xE000E100
197 #endif /* HW_REGS_H_ */