3 This file is part of the OpenARMWare.
4 Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #define CRYSTAL_FREQ 16000000UL
25 #define CRYSTAL_CODE 0x15 /* 16 MHz */
27 #define PIOSC_FREQ 16000000UL
29 void sysclk_set_rawclock(void){
31 tmp_rcc = 0; //HW_REG(SYSCTL_BASE+RCC_OFFSET);
32 tmp_rcc &= ~(_BV(RCC_IOSCDIS) | _BV(RCC_MOSCDIS) | _BV(RCC_USESYSDIV));
33 tmp_rcc |= _BV(RCC_BYPASS) | _BV(RCC_PWRDN);
34 tmp_rcc &= ~(3<<RCC_OSCSRC);
35 tmp_rcc |= (0<<RCC_OSCSRC);
36 HW_REG(SYSCTL_BASE+RCC_OFFSET) = tmp_rcc;
37 HW_REG(SYSCTL_BASE+RCC2_OFFSET) &= ~(_BV(31));
41 void sysclk_mosc_verify_enable(void){
42 HW_REG(SYSCTL_BASE+MOSCCTL_OFFSET) |= 1; // turn on main oscillator verify circuit
45 void sysclk_mosc_verify_disable(void){
46 HW_REG(SYSCTL_BASE+MOSCCTL_OFFSET) &= ~1UL; // turn on main oscillator verify circuit
49 void sysclk_set_80MHz(void){
50 uint32_t rcc1, rcc2=0;
51 sysclk_set_rawclock();
52 rcc1 = HW_REG(SYSCTL_BASE+RCC_OFFSET);
53 // rcc2 = HW_REG(SYSCTL_BASE+RCC2_OFFSET);
54 rcc1 &= ~(0x1f<<RCC_XTAL);
55 rcc1 |= CRYSTAL_CODE<<RCC_XTAL;
56 rcc2 = _BV(RCC2_USERCC2) | _BV(RCC2_PWRDN2) | _BV(RCC2_BYPASS2) | _BV(RCC2_USBPWRDN); /* OSCSRC2 is set to 0 */
57 HW_REG(SYSCTL_BASE+RCC_OFFSET) = rcc1;
58 HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
59 rcc2 &= ~_BV(RCC2_PWRDN2);
60 HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
61 rcc2 |= _BV(RCC2_DIV400) | 0x04<<RCC2_SYSDIV2LSB;
62 HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
63 while(!(HW_REG(SYSCTL_BASE+RIS_OFFSET)&_BV(RIS_PLLLRIS))){
65 rcc2 &= ~_BV(RCC2_BYPASS2);
66 HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
69 uint32_t sysclk_get_freq(void){
70 uint32_t rcc1, rcc2, basefreq=400000000UL, divider=1;
71 const uint32_t bypass_freq[] = {
72 CRYSTAL_FREQ, PIOSC_FREQ, PIOSC_FREQ/4, 30000,
73 0, 0, 4194304, 32768 };
74 rcc1 = HW_REG(SYSCTL_BASE+RCC_OFFSET);
75 rcc2 = HW_REG(SYSCTL_BASE+RCC2_OFFSET);
76 if(rcc2&_BV(RCC2_USERCC2)){
78 if(rcc2&_BV(RCC2_BYPASS2)){
79 basefreq = bypass_freq[(rcc2>>RCC2_OSCSR2)&0x07];
81 if(rcc2&_BV(RCC2_DIV400)){
82 divider = ((rcc2>>RCC2_SYSDIV2LSB)&0x7F)+1;
84 divider = ((rcc2>>RCC2_SYSDIV2)&0x3F)+1;
88 if(rcc1&_BV(RCC_BYPASS)){
89 basefreq = bypass_freq[(rcc1>>RCC_OSCSRC)&0x03];
91 divider = ((rcc1>>RCC_SYSDIV)&0xf)+1;
93 return basefreq/divider;