3 This file is part of the OpenARMWare.
4 Copyright (C) 2010 Daniel Otte (daniel.otte@rub.de)
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #define RAM_START 0x20000000
25 #define RAM_SIZE (96*1024)
30 /* the following are defined by the linker */
32 extern char _text_end;
34 extern char _data_end;
38 typedef void(*isr_fpt)(void);
40 static void fault_isr(void){
45 static void default_isr(void){
51 static void nmi_isr(void){
57 memcpy(&_data, &_text_end, &_data_end - &_data);
58 memset(&_bss, 0, &_bss_end - &_bss);
62 isr_fpt isr_vector[] __attribute__ ((section(".isr_vectors"))) = {
63 (isr_fpt)(RAM_START+RAM_SIZE-4),
64 reset_isr, /* Reset */
65 nmi_isr, /* Non-Maskable Interrupt (NMI) */
66 fault_isr, /* Hard Fault */
67 default_isr, /* Memory Management */
68 fault_isr, /* Bus Fault */
69 fault_isr, /* Usage Fault */
74 default_isr, /* SVCall */
75 default_isr, /* Debug Monitor */
77 default_isr, /* PendSV */
78 default_isr, /* SysTick */
79 default_isr, /* GPIO Port A */
80 default_isr, /* GPIO Port B */
81 default_isr, /* GPIO Port C */
82 default_isr, /* GPIO Port D */
83 default_isr, /* GPIO Port E */
84 uart0_isr, /* UART0 */
85 // default_isr, /* UART0 */
86 default_isr, /* UART1 */
87 default_isr, /* SSI0 */
88 default_isr, /* I2C0 */
94 default_isr, /* ADC0 Sequence 0 */
95 default_isr, /* ADC0 Sequence 1 */
96 default_isr, /* ADC0 Sequence 2 */
97 default_isr, /* ADC0 Sequence 3 */
98 default_isr, /* Watchdog Timers 0 and 1 */
99 default_isr, /* Timer 0A */
100 default_isr, /* Timer 0B */
101 default_isr, /* Timer 1A */
102 default_isr, /* Timer 1B */
103 default_isr, /* Timer 2A */
104 default_isr, /* Timer 2B */
105 default_isr, /* Analog Comparator 0 */
106 default_isr, /* Analog Comparator 1 */
107 default_isr, /* Analog Comparator 2 */
108 default_isr, /* System Control */
109 default_isr, /* Flash Memory Control */
110 default_isr, /* GPIO Port F */
111 default_isr, /* GPIO Port G */
112 default_isr, /* GPIO Port H */
113 default_isr, /* UART2 */
114 default_isr, /* SSI1 */
115 default_isr, /* Timer 3A */
116 default_isr, /* Timer 3B */
117 default_isr, /* I2C1 */
119 default_isr, /* CAN0 */
120 default_isr, /* CAN1 */
122 default_isr, /* Ethernet Controller */
123 default_isr, /* Hibernation Module */
124 default_isr, /* USB */
126 default_isr, /* µDMA Software */
127 default_isr, /* µDMA Error */
128 default_isr, /* ADC1 Sequence 0 */
129 default_isr, /* ADC1 Sequence 1 */
130 default_isr, /* ADC1 Sequence 2 */
131 default_isr, /* ADC1 Sequence 3 */
132 default_isr, /* I2S0 */
133 default_isr, /* EPI */
134 default_isr, /* GPIO Port J */