From 3a80fbe29e33b818ccebbaba7f8bbe48c5ccd173 Mon Sep 17 00:00:00 2001
From: bg <daniel.otte@rub.de>
Date: Tue, 18 Sep 2012 20:29:48 +0200
Subject: [PATCH] forgotten bmw stuff

---
 bmw/autogen_f0_asm.rb           |   449 +
 bmw/autogen_f0_asmmix.rb        |   487 +
 bmw/autogen_f1_neon_small.rb    |   213 +
 bmw/bmw_small-asm-cstub.c       |   544 +
 bmw/bmw_small-asm-cstub.s       |  1275 +++
 bmw/bmw_small-asm.S             |   220 +
 bmw/bmw_small_speed.s           |  1994 ++++
 bmw/bmw_small_speed_asm_f0.S    |   118 +
 bmw/bmw_small_speed_asmmix_f0.S |    71 +
 bmw/bmw_small_speed_cstub.c     |   339 +
 bmw/bmw_small_speed_neon.s      | 17268 ++++++++++++++++++++++++++++++
 bmw/f0_small_autogen.i          |   207 +
 bmw/f0_small_autogen_mix.i      |   227 +
 bmw/f1_autogen_neon_small.i     |   330 +
 bmw/gen_f0_arm.rb               |    59 +
 15 files changed, 23801 insertions(+)
 create mode 100644 bmw/autogen_f0_asm.rb
 create mode 100644 bmw/autogen_f0_asmmix.rb
 create mode 100644 bmw/autogen_f1_neon_small.rb
 create mode 100644 bmw/bmw_small-asm-cstub.c
 create mode 100644 bmw/bmw_small-asm-cstub.s
 create mode 100644 bmw/bmw_small-asm.S
 create mode 100644 bmw/bmw_small_speed.s
 create mode 100644 bmw/bmw_small_speed_asm_f0.S
 create mode 100644 bmw/bmw_small_speed_asmmix_f0.S
 create mode 100644 bmw/bmw_small_speed_cstub.c
 create mode 100644 bmw/bmw_small_speed_neon.s
 create mode 100644 bmw/f0_small_autogen.i
 create mode 100644 bmw/f0_small_autogen_mix.i
 create mode 100644 bmw/f1_autogen_neon_small.i
 create mode 100644 bmw/gen_f0_arm.rb

diff --git a/bmw/autogen_f0_asm.rb b/bmw/autogen_f0_asm.rb
new file mode 100644
index 0000000..6ff7c22
--- /dev/null
+++ b/bmw/autogen_f0_asm.rb
@@ -0,0 +1,449 @@
+# autogen_f0_asm.rb 
+=begin
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+=end
+=begin
+  tmp = +t[ 5] +t[10] +t[13] +(tr1=-t[ 7]+t[14]) ;
+  q[ 0] = S32_0(tmp) + h[ 1];
+  tmp = +t[ 8] +t[13] +t[ 0] -(tr2=+t[ 1]+t[10]) ;
+  q[ 3] = S32_3(tmp) + h[ 4];
+  tmp = -t[11] +t[13] -t[ 0] -t[ 3] +t[ 4] ;
+  q[ 6] = S32_1(tmp) + h[ 7];
+  tmp = +t[ 0] +(tr0=-t[ 3]+t[ 6]) +(tr1) ;
+  q[ 9] = S32_4(tmp) + h[10];
+  tmp = -t[ 9] -(tr0) +(tr2) ;
+  q[12] = S32_2(tmp) + h[13];
+  tmp = -t[ 4] +(tr0=-t[ 9]+t[12]) +(tr1=-t[ 6]+t[13]) ;
+  q[15] = S32_0(tmp) + h[ 0];
+  tmp = +t[ 7] +t[15] +t[ 0] -(tr0) ;
+  q[ 2] = S32_2(tmp) + h[ 3];
+  tmp = +t[10] +(tr0=-t[ 2]+t[15]) +(tr2=+t[ 3]-t[12]) ;
+  q[ 5] = S32_0(tmp) + h[ 6];
+  tmp = -t[ 5] -(tr0) +(tr1) ;
+  q[ 8] = S32_3(tmp) + h[ 9];
+  tmp = -t[ 0] -t[ 2] +t[ 9] +(tr0=-t[ 5]+t[ 8]) ;
+  q[11] = S32_1(tmp) + h[12];
+  tmp = -t[11] +(tr0) +(tr2) ;
+  q[14] = S32_4(tmp) + h[15];
+  tmp = +t[ 6] +(tr0=+t[11]+t[14]) -(tr1=+t[ 8]+t[15]) ;
+  q[ 1] = S32_1(tmp) + h[ 2];
+  tmp = +t[ 9] +t[ 1] +t[ 2] -(tr0) ;
+  q[ 4] = S32_4(tmp) + h[ 5];
+  tmp = -t[12] -t[14] +t[ 1] -t[ 4] -t[ 5] ;
+  q[ 7] = S32_2(tmp) + h[ 8];
+  tmp = -t[ 1] -(tr0=+t[ 4]+t[ 7]) +(tr1) ;
+  q[10] = S32_0(tmp) + h[11];
+  tmp = +t[ 2] +t[10] +t[11] +(tr0) ;
+  q[13] = S32_3(tmp) + h[14];
+=end
+$c_code = <<EOF
+  tmp = +t[ 5] +t[10] +t[13] +(tr1=-t[ 7]+t[14]) ;
+  q[ 0] = S32_0(tmp) + h[ 1];
+  tmp = +t[ 8] +t[13] +t[ 0] -(tr2=+t[ 1]+t[10]) ;
+  q[ 3] = S32_3(tmp) + h[ 4];
+  tmp = -t[11] +t[13] -t[ 0] -t[ 3] +t[ 4] ;
+  q[ 6] = S32_1(tmp) + h[ 7];
+  tmp = +t[ 0] +(tr0=-t[ 3]+t[ 6]) +(tr1) ;
+  q[ 9] = S32_4(tmp) + h[10];
+  tmp = -t[ 9] -(tr0) +(tr2) ;
+  q[12] = S32_2(tmp) + h[13];
+  tmp = -t[ 4] +(tr0=-t[ 9]+t[12]) +(tr1=-t[ 6]+t[13]) ;
+  q[15] = S32_0(tmp) + h[ 0];
+  tmp = +t[ 7] +t[15] +t[ 0] -(tr0) ;
+  q[ 2] = S32_2(tmp) + h[ 3];
+  tmp = +t[10] +(tr0=-t[ 2]+t[15]) +(tr2=+t[ 3]-t[12]) ;
+  q[ 5] = S32_0(tmp) + h[ 6];
+  tmp = -t[ 5] -(tr0) +(tr1) ;
+  q[ 8] = S32_3(tmp) + h[ 9];
+  tmp = -t[ 0] -t[ 2] +t[ 9] +(tr0=-t[ 5]+t[ 8]) ;
+  q[11] = S32_1(tmp) + h[12];
+  tmp = -t[11] +(tr0) +(tr2) ;
+  q[14] = S32_4(tmp) + h[15];
+  tmp = +t[ 6] +(tr0=+t[11]+t[14]) -(tr1=+t[ 8]+t[15]) ;
+  q[ 1] = S32_1(tmp) + h[ 2];
+  tmp = +t[ 9] +t[ 1] +t[ 2] -(tr0) ;
+  q[ 4] = S32_4(tmp) + h[ 5];
+  tmp = -t[12] -t[14] +t[ 1] -t[ 4] -t[ 5] ;
+  q[ 7] = S32_2(tmp) + h[ 8];
+  tmp = -t[ 1] -(tr0=+t[ 4]+t[ 7]) +(tr1) ;
+  q[10] = S32_0(tmp) + h[11];
+  tmp = +t[ 2] +t[10] +t[11] +(tr0) ;
+  q[13] = S32_3(tmp) + h[14];
+EOF
+
+$registers = ["r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14"].reverse
+
+class Array
+  def chopf(n=1)
+    return self[n..-1]
+  end
+end
+
+class String
+  def chopf(n=1)
+    return self[n..-1]
+  end
+end
+
+
+class Operation
+  attr_reader :read_t
+  attr_reader :read_tr
+  attr_reader :write_tr0, :write_tr1, :write_tr2 
+  attr_reader :index, :s, :h
+
+  def init
+    @read_t = Array.new
+    @read_tr = Array.new
+    @write_tr0 = Array.new
+    @write_tr1 = Array.new
+    @write_tr2 = Array.new
+    @index = -1
+    @s = -1
+    @h = -1
+  end
+  
+  def parse(line)
+    s = line
+    while m = /([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @read_t << m[1]+m[2]
+      s = m[3]
+    end
+    s = line
+    while m = /([+-])\(tr([012])(.*)/.match(s)
+      @read_tr << m[1]+m[2]
+      s = m[3]
+    end
+    s = line
+    while m = /tr0=([+-])t\[[\s]*([\d]*)\][\s]*([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @write_tr0 << m[1]+m[2]
+      @write_tr0 << m[3]+m[4]
+      s = m[5]
+    end
+    s = line
+    while m = /tr1=([+-])t\[[\s]*([\d]*)\][\s]*([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @write_tr1 << m[1]+m[2]
+      @write_tr1 << m[3]+m[4]
+      s = m[5]
+    end
+    s = line
+    while m = /tr2=([+-])t\[[\s]*([\d]*)\][\s]*([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @write_tr2 << m[1]+m[2]
+      @write_tr2 << m[3]+m[4]
+      s = m[5]
+    end
+    if m=/q\[[\s]*([\d]*)\]/m.match(line)
+      @index = m[1].to_i
+    end
+    if m=/S32_([0-4])\(tmp\)/m.match(line)
+      @s = m[1].to_i
+    end
+    if m=/h\[[\s]*([\d]*)\]/m.match(line)
+      @h = m[1].to_i
+    end
+  end
+  
+end
+
+
+$operations = Array.new
+
+def parse_c_code
+  i=0
+  s = ''
+  $c_code.each_line do |line|
+#    puts "DBG: line=", line
+    if /^[\s]*tmp/.match(line)
+      s = line
+    end
+    if /^[\s]*q\[[\s\d\]]/.match(line)
+      s += line 
+      $operations[i] = Operation.new
+      $operations[i].init
+      $operations[i].parse(s)
+      i+=1
+    end
+  end
+end
+
+class Array
+  def getsmallest(i=0)
+    tmp = self.sort
+    tmp.each {|x| return x if x>i}
+    return nil
+  end
+  
+  def getlargestindex
+    return self.index(nil) if self.index(nil)
+    tmp = self.sort
+    return self.index(tmp[-1])
+  end
+end
+
+def find_register_to_free(registermap, regusemap, step)
+  if i=registermap.index(nil)
+    return i
+  end
+  tmp = Array.new
+  registermap.each do |x|
+    if x!='x' and regusemap[x.to_i.abs]
+      t = regusemap[x.to_i.abs].getsmallest(step)
+      tmp << t
+    else
+      tmp << -1
+    end
+  end
+  return tmp.getlargestindex
+end
+
+def unused_registers(regoccupation, operation)
+  tmp = Array.new
+  tmp2 = Array.new
+  t = Array.new
+  operation.read_t.each do |x|
+    t << x.chopf
+  end
+  regoccupation.each do |x|
+    tmp << x if t.index(x)==nil
+  end
+  regoccupation.each do |x|
+    tmp2 << x if tmp.index(x)==nil
+  end
+  
+  return tmp,tmp2
+end
+
+def load_registers(regmap, to_load, step)
+  asm_out = ''
+  to_load2 = Array.new
+  # set to_load2 to all registers which are not already loaded
+#  puts "DBG(a): "+regmap.inspect
+  to_load.each do |x|
+    x = x.to_i.abs
+    to_load2 << x if regmap.index(x)==nil
+  end
+  to_load2.each do 
+    regmap[find_register_to_free(regmap, $regusemap, step)] = 'x'
+  end
+  to_load2.sort!
+=begin
+  to_load2.length.times do |i|
+    if to_load2[i] and (to_load2[i]+1 == to_load2[i+1])
+      t1 = regmap.index('x')
+      regmap[t1] = to_load2[i].to_s
+      t2 = regmap.index('x')
+      regmap[t2] = to_load2[i+1].to_s
+      asm_out += sprintf("  ldrd %s, %s, T%02d_ADDR\n", $registers[t1], $registers[t2], to_load2[i+1])
+#     asm_out += sprintf("  ldr %s, T%02d_ADDR\n", $registers[t1], x)
+#      asm_out += sprintf("  ldr %s, T%02d_ADDR\n", $registers[t2], x)
+      to_load2[i] = nil
+      
+      to_load2[i+1] = nil
+    end
+  end
+=end
+  to_load2.delete(nil)
+  to_load2.each do |x|
+    y = regmap.index('x')
+    puts "Strange error!\n" if not y
+    regmap[y]=x.to_s
+    asm_out += sprintf("  ldr %s, T%02d_ADDR\n", $registers[y], x)
+  end
+#  puts asm_out
+#  puts "DBG(0): "+regmap.inspect
+#  puts "DBG(1): "+to_load.inspect
+#  puts "DBG(2): "+to_load2.inspect
+  return regmap, asm_out
+end
+
+def gen_simple_assembler(operations)
+  asm_out=''
+  accu = $registers.length-4
+#  outr = $registers.length-4
+  tr0 =  $registers.length-3
+  tr1 =  $registers.length-2
+  tr2 =  $registers.length-1
+  
+  reg_cnt = $registers.length-4
+  regmap = Array.new(reg_cnt)
+  reg_idx=0
+  step = 0
+  operations.each do |op|
+    asm_out += sprintf("/*=== W[%2d] ===*/\n", op.index)
+    regmap, tstr = load_registers(regmap, op.read_t, step-1)
+    asm_out += tstr
+    step += 1
+    reg_hash = Hash.new
+    op.read_t.each do |t|
+      if regmap.index(t.chopf)==nil
+        printf("ERROR: too few registers!\n")
+      end
+      reg_hash[t.chopf]=regmap.index(t.chopf)
+    end
+    if op.write_tr0.length==2
+      signs_code=op.write_tr0[0][0..0]+op.write_tr0[1][0..0]
+      case signs_code
+        when "++"
+          asm_out += sprintf("  add %s, %s, %s\n", $registers[tr0], \
+            $registers[reg_hash[op.write_tr0[0].chopf]], \
+            $registers[reg_hash[op.write_tr0[1].chopf]])  
+        when "+-"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[tr0], \
+            $registers[reg_hash[op.write_tr0[0].chopf]], \
+            $registers[reg_hash[op.write_tr0[1].chopf]])  
+        when "-+"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[tr0], \
+            $registers[reg_hash[op.write_tr0[1].chopf]], \
+            $registers[reg_hash[op.write_tr0[0].chopf]])  
+        else
+          printf("ERROR: invalid signs_code (%d): %s\n", __LINE__, signs_code)
+          puts op.inspect
+      end
+    end
+    if op.write_tr1.length==2
+      signs_code=op.write_tr1[0][0..0]+op.write_tr1[1][0..0]
+      case signs_code
+        when "++"
+          asm_out += sprintf("  add %s, %s, %s\n", $registers[tr1], \
+            $registers[reg_hash[op.write_tr1[0].chopf]], \
+            $registers[reg_hash[op.write_tr1[1].chopf]])  
+        when "+-"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[tr1], \
+            $registers[reg_hash[op.write_tr1[0].chopf]], \
+            $registers[reg_hash[op.write_tr1[1].chopf]])  
+        when "-+"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[tr1], \
+            $registers[reg_hash[op.write_tr1[1].chopf]], \
+            $registers[reg_hash[op.write_tr1[0].chopf]])  
+        else
+          printf("ERROR: invalid signs_code (%d): %s\n", __LINE__, signs_code)
+          puts op.inspect
+      end
+    end
+    if op.write_tr2.length==2
+      signs_code=op.write_tr2[0][0..0]+op.write_tr2[1][0..0]
+      case signs_code
+        when "++"
+          asm_out += sprintf("  add %s, %s, %s\n", $registers[tr2], \
+            $registers[reg_hash[op.write_tr2[0].chopf]], \
+            $registers[reg_hash[op.write_tr2[1].chopf]])  
+        when "+-"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[tr2], \
+            $registers[reg_hash[op.write_tr2[0].chopf]], \
+            $registers[reg_hash[op.write_tr2[1].chopf]])  
+        when "-+"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[tr2], \
+            $registers[reg_hash[op.write_tr2[1].chopf]], \
+            $registers[reg_hash[op.write_tr2[0].chopf]])  
+        else
+          printf("ERROR: invalid signs_code (%d): %s\n", __LINE__, signs_code)
+          puts op.inspect
+      end
+    end
+    reg_hash['0tr'] = tr0
+    reg_hash['1tr'] = tr1
+    reg_hash['2tr'] = tr2
+    operations_to_do = op.read_t
+    op.read_tr.each {|x| operations_to_do << x+'tr'}
+    op.write_tr0.each {|x| operations_to_do.delete(x)}
+    op.write_tr1.each {|x| operations_to_do.delete(x)}
+    op.write_tr2.each {|x| operations_to_do.delete(x)}
+    operations_to_do = operations_to_do.sort
+    asm_out += sprintf("/*(-- should do %s --)*/\n", operations_to_do.join(', '));
+    sign_code=operations_to_do[1][0..0]
+    case sign_code
+      when '+'
+        asm_out += sprintf("  add %s, %s, %s\n", $registers[accu], \
+          $registers[reg_hash[operations_to_do[0].chopf]], \
+          $registers[reg_hash[operations_to_do[1].chopf]])           
+      when '-'
+        asm_out += sprintf("  sub %s, %s, %s\n", $registers[accu], \
+          $registers[reg_hash[operations_to_do[0].chopf]], \
+          $registers[reg_hash[operations_to_do[1].chopf]])
+    end
+    operations_to_do = operations_to_do[2..-1]
+    operations_to_do.each do |x|
+      sign_code=x[0..0]
+      case sign_code
+        when '+'
+          asm_out += sprintf("  add %s, %s\n", $registers[accu], \
+            $registers[reg_hash[x.chopf]])           
+        when '-'
+          asm_out += sprintf("  sub %s, %s\n", $registers[accu], \
+            $registers[reg_hash[x.chopf]])
+      end      
+    end
+    outr = find_register_to_free(regmap, $regusemap, step)
+    regmap[outr]=nil
+    if(op.s==4)
+      asm_out += sprintf("  S32_4 %s\n", $registers[accu])
+      asm_out += sprintf("  ldr %s, [r1, #%d*4]\n", $registers[outr], op.h)
+      asm_out += sprintf("  add %s, %s\n", $registers[accu], $registers[outr])
+      asm_out += sprintf("  str %s, [r0, #%d*4]\n", $registers[accu], op.index)
+    else
+      asm_out += sprintf("  S32_%d %s %s\n", op.s, $registers[outr], $registers[accu])
+      asm_out += sprintf("  ldr %s, [r1, #%d*4]\n", $registers[accu], op.h)      
+      asm_out += sprintf("  add %s, %s\n", $registers[outr], $registers[accu])
+      asm_out += sprintf("  str %s, [r0, #%d*4]\n", $registers[outr], op.index)
+    end
+
+#  asm_out += sprintf("  str %s, [r0, #%d*4]\n", $registers[accu], op.index)    
+  end
+  return asm_out
+end
+
+class RegMapEntry
+  attr_accessor :usemap
+  attr_accessor :nextusemap
+end
+=begin
+class RegMap
+  atrr_reader :steps
+  atrr_reader :entrys
+  attr_reader :regcnt
+end
+
+def gen_regmap_simple
+  
+end
+=end
+$regusemap = Array.new
+
+def build_regusemap(operations)
+  i=0
+  operations.each do |op|
+    op.read_t.each do |t|
+      x = t.chopf.to_i
+      if $regusemap[x]==nil
+        $regusemap[x]=Array.new
+      end
+      $regusemap[x]<<i
+    end
+    i += 1
+  end
+end
+
+#-------------------------------------------------------------------------------
+# MAIN
+#-------------------------------------------------------------------------------
+
+parse_c_code
+#puts $operations.inspect
+build_regusemap($operations)
+#puts $regusemap.inspect
+puts gen_simple_assembler($operations)
+
diff --git a/bmw/autogen_f0_asmmix.rb b/bmw/autogen_f0_asmmix.rb
new file mode 100644
index 0000000..1da0126
--- /dev/null
+++ b/bmw/autogen_f0_asmmix.rb
@@ -0,0 +1,487 @@
+# autogen_f0_asm.rb 
+=begin
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+=end
+=begin
+  tmp = +t[ 5] +t[10] +t[13] +(tr1=-t[ 7]+t[14]) ;
+  q[ 0] = S32_0(tmp) + h[ 1];
+  tmp = +t[ 8] +t[13] +t[ 0] -(tr2=+t[ 1]+t[10]) ;
+  q[ 3] = S32_3(tmp) + h[ 4];
+  tmp = -t[11] +t[13] -t[ 0] -t[ 3] +t[ 4] ;
+  q[ 6] = S32_1(tmp) + h[ 7];
+  tmp = +t[ 0] +(tr0=-t[ 3]+t[ 6]) +(tr1) ;
+  q[ 9] = S32_4(tmp) + h[10];
+  tmp = -t[ 9] -(tr0) +(tr2) ;
+  q[12] = S32_2(tmp) + h[13];
+  tmp = -t[ 4] +(tr0=-t[ 9]+t[12]) +(tr1=-t[ 6]+t[13]) ;
+  q[15] = S32_0(tmp) + h[ 0];
+  tmp = +t[ 7] +t[15] +t[ 0] -(tr0) ;
+  q[ 2] = S32_2(tmp) + h[ 3];
+  tmp = +t[10] +(tr0=-t[ 2]+t[15]) +(tr2=+t[ 3]-t[12]) ;
+  q[ 5] = S32_0(tmp) + h[ 6];
+  tmp = -t[ 5] -(tr0) +(tr1) ;
+  q[ 8] = S32_3(tmp) + h[ 9];
+  tmp = -t[ 0] -t[ 2] +t[ 9] +(tr0=-t[ 5]+t[ 8]) ;
+  q[11] = S32_1(tmp) + h[12];
+  tmp = -t[11] +(tr0) +(tr2) ;
+  q[14] = S32_4(tmp) + h[15];
+  tmp = +t[ 6] +(tr0=+t[11]+t[14]) -(tr1=+t[ 8]+t[15]) ;
+  q[ 1] = S32_1(tmp) + h[ 2];
+  tmp = +t[ 9] +t[ 1] +t[ 2] -(tr0) ;
+  q[ 4] = S32_4(tmp) + h[ 5];
+  tmp = -t[12] -t[14] +t[ 1] -t[ 4] -t[ 5] ;
+  q[ 7] = S32_2(tmp) + h[ 8];
+  tmp = -t[ 1] -(tr0=+t[ 4]+t[ 7]) +(tr1) ;
+  q[10] = S32_0(tmp) + h[11];
+  tmp = +t[ 2] +t[10] +t[11] +(tr0) ;
+  q[13] = S32_3(tmp) + h[14];
+=end
+$c_code = <<EOF
+  tmp = +t[ 5] +t[10] +t[13] +(tr1=-t[ 7]+t[14]) ;
+  q[ 0] = S32_0(tmp) + h[ 1];
+  tmp = +t[ 8] +t[13] +t[ 0] -(tr2=+t[ 1]+t[10]) ;
+  q[ 3] = S32_3(tmp) + h[ 4];
+  tmp = -t[11] +t[13] -t[ 0] -t[ 3] +t[ 4] ;
+  q[ 6] = S32_1(tmp) + h[ 7];
+  tmp = +t[ 0] +(tr0=-t[ 3]+t[ 6]) +(tr1) ;
+  q[ 9] = S32_4(tmp) + h[10];
+  tmp = -t[ 9] -(tr0) +(tr2) ;
+  q[12] = S32_2(tmp) + h[13];
+  tmp = -t[ 4] +(tr0=-t[ 9]+t[12]) +(tr1=-t[ 6]+t[13]) ;
+  q[15] = S32_0(tmp) + h[ 0];
+  tmp = +t[ 7] +t[15] +t[ 0] -(tr0) ;
+  q[ 2] = S32_2(tmp) + h[ 3];
+  tmp = +t[10] +(tr0=-t[ 2]+t[15]) +(tr2=+t[ 3]-t[12]) ;
+  q[ 5] = S32_0(tmp) + h[ 6];
+  tmp = -t[ 5] -(tr0) +(tr1) ;
+  q[ 8] = S32_3(tmp) + h[ 9];
+  tmp = -t[ 0] -t[ 2] +t[ 9] +(tr0=-t[ 5]+t[ 8]) ;
+  q[11] = S32_1(tmp) + h[12];
+  tmp = -t[11] +(tr0) +(tr2) ;
+  q[14] = S32_4(tmp) + h[15];
+  tmp = +t[ 6] +(tr0=+t[11]+t[14]) -(tr1=+t[ 8]+t[15]) ;
+  q[ 1] = S32_1(tmp) + h[ 2];
+  tmp = +t[ 9] +t[ 1] +t[ 2] -(tr0) ;
+  q[ 4] = S32_4(tmp) + h[ 5];
+  tmp = -t[12] -t[14] +t[ 1] -t[ 4] -t[ 5] ;
+  q[ 7] = S32_2(tmp) + h[ 8];
+  tmp = -t[ 1] -(tr0=+t[ 4]+t[ 7]) +(tr1) ;
+  q[10] = S32_0(tmp) + h[11];
+  tmp = +t[ 2] +t[10] +t[11] +(tr0) ;
+  q[13] = S32_3(tmp) + h[14];
+EOF
+
+$registers = ["r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14"].reverse
+
+class Array
+  def chopf(n=1)
+    return self[n..-1]
+  end
+end
+
+class String
+  def chopf(n=1)
+    return self[n..-1]
+  end
+  
+  def is_numeric?(b=10)
+    n=self.to_i(b)
+    s=n.to_s(b)
+    (self==s) or (self==('+'+s))
+  end
+  
+  def xtr
+    return self.to_i if self.is_numeric?
+    self
+  end
+end
+
+
+class Operation
+  attr_reader :read_t
+  attr_reader :read_tr
+  attr_reader :write_tr0, :write_tr1, :write_tr2 
+  attr_reader :index, :s, :h
+
+  def init
+    @read_t = Array.new
+    @read_tr = Array.new
+    @write_tr0 = Array.new
+    @write_tr1 = Array.new
+    @write_tr2 = Array.new
+    @index = -1
+    @s = -1
+    @h = -1
+  end
+  
+  def parse(line)
+    s = line
+    while m = /([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @read_t << m[1]+m[2]
+      s = m[3]
+    end
+    s = line
+    while m = /([+-])\(tr([012])(.*)/.match(s)
+      @read_tr << m[1]+m[2]
+      s = m[3]
+    end
+    s = line
+    while m = /tr0=([+-])t\[[\s]*([\d]*)\][\s]*([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @write_tr0 << m[1]+m[2]
+      @write_tr0 << m[3]+m[4]
+      s = m[5]
+    end
+    s = line
+    while m = /tr1=([+-])t\[[\s]*([\d]*)\][\s]*([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @write_tr1 << m[1]+m[2]
+      @write_tr1 << m[3]+m[4]
+      s = m[5]
+    end
+    s = line
+    while m = /tr2=([+-])t\[[\s]*([\d]*)\][\s]*([+-])t\[[\s]*([\d]*)\](.*)/.match(s)
+      @write_tr2 << m[1]+m[2]
+      @write_tr2 << m[3]+m[4]
+      s = m[5]
+    end
+    if m=/q\[[\s]*([\d]*)\]/m.match(line)
+      @index = m[1].to_i
+    end
+    if m=/S32_([0-4])\(tmp\)/m.match(line)
+      @s = m[1].to_i
+    end
+    if m=/h\[[\s]*([\d]*)\]/m.match(line)
+      @h = m[1].to_i
+    end
+  end
+  
+end
+
+
+$operations = Array.new
+
+def parse_c_code
+  i=0
+  s = ''
+  $c_code.each_line do |line|
+#    puts "DBG: line=", line
+    if /^[\s]*tmp/.match(line)
+      s = line
+    end
+    if /^[\s]*q\[[\s\d\]]/.match(line)
+      s += line 
+      $operations[i] = Operation.new
+      $operations[i].init
+      $operations[i].parse(s)
+      i+=1
+    end
+  end
+end
+
+class Array
+  def getsmallest(i=0)
+    tmp = self.sort
+    tmp.each {|x| return x if x>i}
+    return nil
+  end
+  
+  def getlargestindex
+    return self.index(nil) if self.index(nil)
+    tmp = self.sort
+    return self.index(tmp[-1])
+  end
+end
+
+def find_register_to_free(registermap, regusemap, step)
+  if i=registermap.index(nil)
+    return i
+  end
+  tmp = Array.new
+  registermap.each do |x|
+    if x.class==Fixnum and regusemap[x.abs]
+      t = regusemap[x.abs].getsmallest(step)
+      tmp << t
+    else
+      tmp << -1
+    end
+  end
+  return tmp.getlargestindex
+end
+
+
+def load_registers(regmap, stack, op, step)
+  asm_out = ''
+  to_load2 = Array.new
+  push_list = Array.new
+  # set to_load2 to all registers which are not already loaded
+#  puts "DBG(a): "+regmap.inspect
+  op.read_t.each do |x|
+    x = x.to_i.abs
+    to_load2 << x if regmap.index(x)==nil
+  end
+  to_load2.each do 
+    regmap[find_register_to_free(regmap, $regusemap, step)] = 'x'
+  end
+  if op.write_tr0.length!=0
+    regmap[find_register_to_free(regmap, $regusemap, step)] = 'tr0'
+  end
+  if op.write_tr1.length!=0
+    regmap[find_register_to_free(regmap, $regusemap, step)] = 'tr1'
+  end
+  if op.write_tr2.length!=0
+    regmap[find_register_to_free(regmap, $regusemap, step)] = 'tr2'
+  end
+  to_load2.sort!
+=begin
+  to_load2.length.times do |i|
+    x = to_load2[i]
+    y = to_load2[i+1]
+    if x and y and (to_load2[i]+1 == to_load2[i+1]) and stack.index(x) and stack.index(y)
+      rx = regmap.index('x')
+      regmap[rx]=x.to_s
+      ry = regmap.index('x')
+      regmap[ry]=y.to_s
+      asm_out += sprintf("  ldrd %s, %s, [SP, #%d*4]\n", $registers[rx], $registers[ry], x)
+      to_load2[i] = nil
+      to_load2[i+1] = nil
+    end
+  end
+=end
+  to_load2.delete(nil)
+  to_load2.each do |x|
+    next if not x
+    y = regmap.index('x')
+    puts "Strange error!\n" if not y
+    regmap[y]=x
+    if stack.index(x)
+      asm_out += sprintf("  ldr %s, [SP, #%d*4]\n", $registers[y], x)
+    else
+      asm_out += sprintf("  ldr %s, [r1, #%d*4]\n", $registers[y], x)
+      asm_out += sprintf("  ldr %s, [r2, #%d*4]\n", $registers[-1], x)
+      asm_out += sprintf("  eor %s, %s\n", $registers[y], $registers[-1])
+      asm_out += sprintf("  str %s, [SP, #%d*4]\n", $registers[y], x)
+      stack << x
+#      push_list << [$registers[y], x]
+    end
+  end
+#  if push_list.length!=0
+#    push_list.sort!{ |x,y| x[0].chopf.to_i <=> y[0].chopf.to_i}
+#    push_regs = push_list.collect {|x| x[0]}
+#    push_list.reverse.each {|x| stack << x[1]}
+#    asm_out += sprintf("  stmdb SP, {%s}\n", push_regs.join(', '))
+#  end
+#  puts asm_out
+#  puts "DBG(0): "+regmap.inspect
+#  puts "DBG(1): "+to_load.inspect
+#  puts "DBG(2): "+to_load2.inspect
+
+  #puts 'DBG('+__LINE__.to_s+'): regmap = '+regmap.inspect
+  return regmap, stack, asm_out
+end
+
+def gen_simple_assembler(operations)
+  asm_out=''
+  stack = Array.new
+  accu = $registers.length-1
+#  outr = $registers.length-4
+#  tr0 =  $registers.length-3
+#  tr1 =  $registers.length-2
+#  tr2 =  $registers.length-4
+  
+  reg_cnt = $registers.length-1
+  regmap = Array.new(reg_cnt)
+  reg_idx=0
+  step = 0
+  asm_out += sprintf("  sub SP, #%d*4\n", 16)
+  operations.each do |op|
+    asm_out += sprintf("/*=== W[%2d] ===*/\n", op.index)
+    regmap, stack, tstr = load_registers(regmap, stack, op, step-1)
+    asm_out += tstr
+    step += 1
+    reg_hash = Hash.new
+    op.read_t.each do |t|
+      if regmap.index(t.chopf.to_i)==nil
+        printf("ERROR: too few registers!\n")
+      end
+      reg_hash[t.chopf.to_i]=regmap.index(t.chopf.to_i)
+    end
+    if op.write_tr0.length==2
+      signs_code=op.write_tr0[0][0..0]+op.write_tr0[1][0..0]
+      case signs_code
+        when "++"
+          asm_out += sprintf("  add %s, %s, %s\n", $registers[regmap.index('tr0')], \
+            $registers[reg_hash[op.write_tr0[0].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr0[1].chopf.to_i]])  
+        when "+-"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[regmap.index('tr0')], \
+            $registers[reg_hash[op.write_tr0[0].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr0[1].chopf.to_i]])  
+        when "-+"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[regmap.index('tr0')], \
+            $registers[reg_hash[op.write_tr0[1].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr0[0].chopf.to_i]])  
+        else
+          printf("ERROR: invalid signs_code (%d): %s\n", __LINE__, signs_code)
+          puts op.inspect
+      end
+    end
+    if op.write_tr1.length==2
+      signs_code=op.write_tr1[0][0..0]+op.write_tr1[1][0..0]
+      case signs_code
+        when "++"
+          asm_out += sprintf("  add %s, %s, %s\n", $registers[regmap.index('tr1')], \
+            $registers[reg_hash[op.write_tr1[0].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr1[1].chopf.to_i]])  
+        when "+-"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[regmap.index('tr1')], \
+            $registers[reg_hash[op.write_tr1[0].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr1[1].chopf.to_i]])  
+        when "-+"
+  #        puts 'DBG: '+reg_hash.inspect
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[regmap.index('tr1')], \
+            $registers[reg_hash[op.write_tr1[1].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr1[0].chopf.to_i]])  
+        else
+          printf("ERROR: invalid signs_code (%d): %s\n", __LINE__, signs_code)
+          puts op.inspect
+      end
+    end
+    if op.write_tr2.length==2
+      signs_code=op.write_tr2[0][0..0]+op.write_tr2[1][0..0]
+      case signs_code
+        when "++"
+          asm_out += sprintf("  add %s, %s, %s\n", $registers[regmap.index('tr2')], \
+            $registers[reg_hash[op.write_tr2[0].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr2[1].chopf.to_i]])  
+        when "+-"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[regmap.index('tr2')], \
+            $registers[reg_hash[op.write_tr2[0].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr2[1].chopf.to_i]])  
+        when "-+"
+          asm_out += sprintf("  sub %s, %s, %s\n", $registers[regmap.index('tr2')], \
+            $registers[reg_hash[op.write_tr2[1].chopf.to_i]], \
+            $registers[reg_hash[op.write_tr2[0].chopf.to_i]])  
+        else
+          printf("ERROR: invalid signs_code (%d): %s\n", __LINE__, signs_code)
+          puts op.inspect
+      end
+    end
+    reg_hash['0tr'] = regmap.index('tr0')
+    reg_hash['1tr'] = regmap.index('tr1')
+    reg_hash['2tr'] = regmap.index('tr2')
+    tr_to_delete = op.read_tr.collect { |x| x.chopf}
+    tr_to_delete.delete('0') if op.write_tr0.length!=0
+    tr_to_delete.delete('1') if op.write_tr1.length!=0
+    tr_to_delete.delete('2') if op.write_tr2.length!=0
+    tr_to_delete.each do |x|
+      y = regmap.index('tr'+x)
+      regmap[y]=nil if y
+ #     puts 'DBG('+__LINE__.to_s+') deleted tr'+x+' @ '+y.to_s
+    end
+    operations_to_do = op.read_t
+    op.read_tr.each {|x| operations_to_do << x+'tr'}
+    op.write_tr0.each {|x| operations_to_do.delete(x)}
+    op.write_tr1.each {|x| operations_to_do.delete(x)}
+    op.write_tr2.each {|x| operations_to_do.delete(x)}
+    operations_to_do = operations_to_do.sort
+    asm_out += sprintf("/*(-- should do %s --)*/\n", operations_to_do.join(', '));
+    sign_code=operations_to_do[1][0..0]
+    case sign_code
+      when '+'
+   #     puts 'DBG('+__LINE__.to_s+'): x='+operations_to_do[0]+' reg_hash='+reg_hash.inspect
+        asm_out += sprintf("  add %s, %s, %s\n", $registers[accu], \
+          $registers[reg_hash[operations_to_do[0].chopf.xtr]], \
+          $registers[reg_hash[operations_to_do[1].chopf.xtr]])           
+      when '-'
+    #    puts 'DBG('+__LINE__.to_s+'): x='+x+' reg_hash='+reg_hash.inspect
+        asm_out += sprintf("  sub %s, %s, %s\n", $registers[accu], \
+          $registers[reg_hash[operations_to_do[0].chopf.xtr]], \
+          $registers[reg_hash[operations_to_do[1].chopf.xtr]])
+    end
+    operations_to_do = operations_to_do[2..-1]
+    operations_to_do.each do |x|
+      sign_code=x[0..0]
+      case sign_code
+        when '+'
+ #         puts 'DBG('+__LINE__.to_s+'): x='+x+' reg_hash='+reg_hash.inspect
+          asm_out += sprintf("  add %s, %s\n", $registers[accu], \
+            $registers[reg_hash[x.chopf.xtr]])           
+        when '-'
+          asm_out += sprintf("  sub %s, %s\n", $registers[accu], \
+            $registers[reg_hash[x.chopf.xtr]])
+      end      
+    end
+    outr = find_register_to_free(regmap, $regusemap, step)
+    regmap[outr]=nil
+    if(op.s==4)
+      asm_out += sprintf("  S32_4 %s\n", $registers[accu])
+      asm_out += sprintf("  ldr %s, [r1, #%d*4]\n", $registers[outr], op.h)
+      asm_out += sprintf("  add %s, %s\n", $registers[accu], $registers[outr])
+      asm_out += sprintf("  str %s, [r0, #%d*4]\n", $registers[accu], op.index)
+    else
+      asm_out += sprintf("  S32_%d %s %s\n", op.s, $registers[outr], $registers[accu])
+      asm_out += sprintf("  ldr %s, [r1, #%d*4]\n", $registers[accu], op.h)      
+      asm_out += sprintf("  add %s, %s\n", $registers[outr], $registers[accu])
+      asm_out += sprintf("  str %s, [r0, #%d*4]\n", $registers[outr], op.index)
+    end
+
+#  asm_out += sprintf("  str %s, [r0, #%d*4]\n", $registers[accu], op.index)    
+  end
+  asm_out += sprintf("  add SP, #%d*4", 16)
+  return asm_out
+end
+
+class RegMapEntry
+  attr_accessor :usemap
+  attr_accessor :nextusemap
+end
+=begin
+class RegMap
+  atrr_reader :steps
+  atrr_reader :entrys
+  attr_reader :regcnt
+end
+
+def gen_regmap_simple
+  
+end
+=end
+$regusemap = Array.new
+
+def build_regusemap(operations)
+  i=0
+  operations.each do |op|
+    op.read_t.each do |t|
+      x = t.chopf.to_i
+      if $regusemap[x]==nil
+        $regusemap[x]=Array.new
+      end
+      $regusemap[x]<<i
+    end
+    i += 1
+  end
+end
+
+#-------------------------------------------------------------------------------
+# MAIN
+#-------------------------------------------------------------------------------
+
+parse_c_code
+#puts $operations.inspect
+build_regusemap($operations)
+#puts $regusemap.inspect
+puts gen_simple_assembler($operations)
+
diff --git a/bmw/autogen_f1_neon_small.rb b/bmw/autogen_f1_neon_small.rb
new file mode 100644
index 0000000..6f6df54
--- /dev/null
+++ b/bmw/autogen_f1_neon_small.rb
@@ -0,0 +1,213 @@
+# autogen f1 function for BMW
+=begin
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+=end
+
+
+header = <<EOF
+/* BEGIN of automatic generated code */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+static inline
+void bmw_small_f1(uint32_t* q, const uint32_t* m, const uint32_t* h){ 
+  uint32_t even, odd;
+  uint32x4_t qq16, qq20, qq24, qq28;
+  uint32x4_t qm0, qm1, qm2;
+  uint32x4_t qk={0x55555550UL, 0x5aaaaaa5UL, 0x5ffffffaUL, 0x6555554fUL};
+  uint32x4_t qkadd={0x15555554UL, 0x15555554UL, 0x15555554UL, 0x15555554UL};
+  uint32x2_t dtmp0;
+  uint32x4x2_t q2tmp0, q2tmp1;   
+EOF
+
+footer = <<EOF
+}
+
+/* END of automatic generated code */
+
+EOF
+
+
+=begin
+  uint32_t r;
+  /* r = 0x05555555*(j+16); */
+  r = (   ROTL32(((uint32_t*)m)[j],      ((j+0))+1  )
+         + ROTL32(((uint32_t*)m)[(j+3)],  ((j+3))+1  )
+         - ROTL32(((uint32_t*)m)[(j+10)], ((j+10))+1 )
+         + k_lut[j]
+       ) ^ ((uint32_t*)h)[(j+7)];
+  r += S32_1(q[j+ 0]) + S32_2(q[j+ 1]) + S32_3(q[j+ 2]) + S32_0(q[j+ 3]) +
+     S32_1(q[j+ 4]) + S32_2(q[j+ 5]) + S32_3(q[j+ 6]) + S32_0(q[j+ 7]) +
+     S32_1(q[j+ 8]) + S32_2(q[j+ 9]) + S32_3(q[j+10]) + S32_0(q[j+11]) +
+     S32_1(q[j+12]) + S32_2(q[j+13]) + S32_3(q[j+14]) + S32_0(q[j+15]);
+=end
+def gen_addElement(i)
+  j = i-16;
+  s  = sprintf("\n  /* addElement for q%d .. q%d */\n", i, i+3);
+  s += sprintf("  qm0 = *((uint32x4_t*)&(m[%2d]));\n", j);
+  s += sprintf("  qm1 = *((uint32x4_t*)&(m[%2d]));\n", j+3);
+  s += sprintf("  qm2 = *((uint32x4_t*)&(m[%2d]));\n", j+10);
+  s += sprintf("  qm0 = veorq_u32(vshlq_u32(qm0,(int32x4_t){%2d, %2d, %2d, %2d}),vshlq_u32(qm0,(int32x4_t){%2d, %2d, %2d, %2d}));\n",
+                  (j+0)%16+1, (j+1)%16+1, (j+2)%16+1, (j+3)%16+1, 
+                  -(32-((j+0)%16+1)), -(32-((j+1)%16+1)), -(32-((j+2)%16+1)), -(32-((j+3)%16+1)))
+  s += sprintf("  qm1 = veorq_u32(vshlq_u32(qm1,(int32x4_t){%2d, %2d, %2d, %2d}),vshlq_u32(qm1,(int32x4_t){%2d, %2d, %2d, %2d}));\n",
+                  (j+3)%16+1, (j+4)%16+1, (j+5)%16+1, (j+6)%16+1,
+                  -(32-((j+3)%16+1)), -(32-((j+4)%16+1)), -(32-((j+5)%16+1)), -(32-((j+6)%16+1)))
+  s += sprintf("  qm2 = veorq_u32(vshlq_u32(qm2,(int32x4_t){%2d, %2d, %2d, %2d}),vshlq_u32(qm2,(int32x4_t){%2d, %2d, %2d, %2d}));\n",
+                  (j+10)%16+1, (j+11)%16+1, (j+12)%16+1, (j+13)%16+1, 
+                  -(32-((j+10)%16+1)), -(32-((j+11)%16+1)), -(32-((j+12)%16+1)), -(32-((j+13)%16+1)))
+  s += sprintf("  qq%d = veorq_u32(vaddq_u32(vaddq_u32(qm0, qm1),vsubq_u32(qk, qm2)), *((uint32x4_t*)&(h[%2d])));\n",
+                  i, (j+7)%16)
+  s += sprintf("  qk = vaddq_u32(qk, qkadd);\n");                
+  return s
+end
+
+=begin
+  r += S32_1(q[j+ 0]) + S32_2(q[j+ 1]) + S32_3(q[j+ 2]) + S32_0(q[j+ 3]) +
+     S32_1(q[j+ 4]) + S32_2(q[j+ 5]) + S32_3(q[j+ 6]) + S32_0(q[j+ 7]) +
+     S32_1(q[j+ 8]) + S32_2(q[j+ 9]) + S32_3(q[j+10]) + S32_0(q[j+11]) +
+     S32_1(q[j+12]) + S32_2(q[j+13]) + S32_3(q[j+14]) + S32_0(q[j+15]);
+ 
+#define S32_0(x) ( (SHR32((x),   1)) ^ \
+                 (SHL32((x),   3)) ^ \
+                 (ROTL32((x),  4)) ^ \
+                 (ROTR32((x), 13)) )
+
+#define S32_1(x) ( (SHR32((x),   1)) ^ \
+                 (SHL32((x),   2)) ^ \
+                 (ROTL32((x),  8)) ^ \
+                 (ROTR32((x),  9)) )
+
+#define S32_2(x) ( (SHR32((x),   2)) ^ \
+                 (SHL32((x),   1)) ^ \
+                 (ROTL32((x), 12)) ^ \
+                 (ROTR32((x),  7)) )
+
+#define S32_3(x) ( (SHR32((x),   2)) ^ \
+                 (SHL32((x),   2)) ^ \
+                 (ROTL32((x), 15)) ^ \
+                 (ROTR32((x),  3)) )
+=end
+
+def gen_expand_1(i)
+  s  = sprintf("\n  /* expand1(%2d) */\n", i)
+  s += sprintf("  qm0 = *((uint32x4_t*)&(q[%2d]));\n", i);
+  s += sprintf("  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),\n" \
+               "                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),\n" \
+               "                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),\n" \
+               "                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}), \n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));\n")
+  s += sprintf("  qm0 = *((uint32x4_t*)&(q[%2d]));\n", i+4);
+  s += sprintf("  qm2 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),\n" \
+               "                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),\n" \
+               "                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),\n" \
+               "                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));\n")
+  s += sprintf("  qm2 = vaddq_u32(qm2, qm1);\n")                                                   
+  s += sprintf("  qm0 = *((uint32x4_t*)&(q[%2d]));\n", i+8);
+  s += sprintf("  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),\n" \
+               "                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),\n" \
+               "                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),\n" \
+               "                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));\n")
+  s += sprintf("  qm2 = vaddq_u32(qm2, qm1);\n")                                                   
+  s += sprintf("  qm0 = *((uint32x4_t*)&(q[%2d]));\n", i+12);
+  s += sprintf("  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),\n" \
+               "                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),\n" \
+               "                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),\n" \
+               "                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),\n" \
+               "                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));\n")
+  s += sprintf("  qm2 = vaddq_u32(qm2, qm1);\n")                                                   
+  s += sprintf("  dtmp0 = vadd_u32(vget_high_u32(qm2), vget_low_u32(qm2));\n")
+  s += sprintf("  q[%2d] = vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1) + vgetq_lane_u32(qq%d, %2d);\n",
+                 i+16, (i+16)&0xFC, i&3)
+  return s
+end
+
+=begin     
+     + ( even =  q[ 2] + q[ 4] + q[ 6]
+               + q[ 8] + q[10] + q[12] + q[14] )
+     + R32_1(q[ 3]) + R32_2(q[ 5]) + R32_3(q[ 7])
+     + R32_4(q[ 9]) + R32_5(q[11]) + R32_6(q[13])
+     + R32_7(q[15]) + S32_4(q[16]) + S32_5(q[17]);
+     + ( odd  =  q[ 3] + q[ 5] + q[ 7]
+               + q[ 9] + q[11] + q[13] + q[15] )
+     + R32_1(q[ 4]) + R32_2(q[ 6]) + R32_3(q[ 8])
+     + R32_4(q[10]) + R32_5(q[12]) + R32_6(q[14])
+     + R32_7(q[16]) + S32_4(q[17]) + S32_5(q[18]);
+
+#define S32_4(x) ( (SHR32((x),   1)) ^ (x))
+#define S32_5(x) ( (SHR32((x),   2)) ^ (x))
+
+#define R32_1(x)   (ROTL32((x),  3))
+#define R32_2(x)   (ROTL32((x),  7))
+#define R32_3(x)   (ROTL32((x), 13))
+#define R32_4(x)   (ROTL32((x), 16))
+#define R32_5(x)   (ROTR32((x), 13))
+#define R32_6(x)   (ROTR32((x),  9))
+#define R32_7(x)   (ROTR32((x),  5))
+=end
+
+def gen_expand_2(i, start)
+  s  = sprintf("\n  /* expand2(%2d) */\n", i)
+  s += sprintf("  q2tmp0 = vld2q_u32(&q[%2d]);\n", i)
+  s += sprintf("  q2tmp1 = vld2q_u32(&q[%2d]);\n", i+8)
+  if i-1<=start
+    s += sprintf("  q2tmp1.val[0] = vsetq_lane_u32(0, q2tmp1.val[0], 3);\n")
+    s += sprintf("  q2tmp0.val[0] = vaddq_u32(q2tmp0.val[0], q2tmp1.val[0]);\n")
+    s += sprintf("  dtmp0 = vadd_u32(vget_high_u32(q2tmp0.val[0]), vget_low_u32(q2tmp0.val[0]));\n")
+    s += sprintf("  %s = vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);\n",(i%2==0)?"even":"odd ")
+  else
+    s += sprintf("  %s += q[%2d] - q[%2d];\n",(i%2==0)?"even":"odd ", i+12, i-2)  
+  end
+  s += sprintf("  q[%2d] = %s + ((q[%2d]>>1)|q[%2d]);\n", i+16, (i%2==0)?"even":"odd ", i+14, i+14)  
+  s += sprintf("  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),\n" \
+               "                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));\n")
+  s += sprintf("  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),\n" \
+               "                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));\n")
+  s += sprintf("  qm1 = vaddq_u32(qm1, qm0);\n")
+  s += sprintf("  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));\n")
+  s += sprintf("  q[%2d] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);\n", i+16)  
+  
+  return s
+end
+
+
+puts header
+[16,20,24,28].each {|x| puts gen_addElement(x)}
+(0..1).each  {|x| puts gen_expand_1(x)}
+(2..15).each {|x| puts gen_expand_2(x, 2)}
+puts footer
\ No newline at end of file
diff --git a/bmw/bmw_small-asm-cstub.c b/bmw/bmw_small-asm-cstub.c
new file mode 100644
index 0000000..04bd59d
--- /dev/null
+++ b/bmw/bmw_small-asm-cstub.c
@@ -0,0 +1,544 @@
+/* bmw_small.c */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+ * \file    bmw_small.c
+ * \author  Daniel Otte
+ * \email   daniel.otte@rub.de
+ * \date    2009-04-27
+ * \license GPLv3 or later
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "bmw_small.h"
+#include "memxor.h"
+
+#define SHL32(a,n) ((a)<<(n))
+#define SHR32(a,n) ((a)>>(n))
+#define ROTL32(a,n) (((a)<<(n))|((a)>>(32-(n))))
+#define ROTR32(a,n) (((a)>>(n))|((a)<<(32-(n))))
+
+
+#define TWEAK   1
+#if TWEAK
+#  define BUG24   0
+#else
+#  define BUG24   1
+#endif
+
+#define F0_HACK 0
+
+#define DEBUG 0
+
+#ifndef F0_HACK
+#  define F0_HACK 0
+#endif
+
+#if DEBUG
+ #include "cli.h"
+
+ void ctx_dump(const bmw_small_ctx_t* ctx){
+ 	uint8_t i;
+	cli_putstr("\r\n==== ctx dump ====");
+	for(i=0; i<16;++i){
+		cli_putstr("\r\n h[");
+		cli_hexdump(&i, 1);
+		cli_putstr("] = ");
+		cli_hexdump_rev(&(ctx->h[i]), 4);
+	}
+	cli_putstr("\r\n counter = ");
+	cli_hexdump(&(ctx->counter), 4);
+ }
+
+ void dump_x(const uint32_t* q, uint8_t elements, char x){
+	uint8_t i;
+ 	cli_putstr("\r\n==== ");
+	cli_putc(x);
+	cli_putstr(" dump ====");
+	for(i=0; i<elements;++i){
+		cli_putstr("\r\n ");
+		cli_putc(x);
+		cli_putstr("[");
+		cli_hexdump(&i, 1);
+		cli_putstr("] = ");
+		cli_hexdump_rev(&(q[i]), 4);
+	}
+ }
+#else
+ #define ctx_dump(x)
+ #define dump_x(a,b,c)
+#endif
+
+#define S32_0(x) ( (SHR32((x),   1)) ^ \
+	               (SHL32((x),   3)) ^ \
+	               (ROTL32((x),  4)) ^ \
+	               (ROTR32((x), 13)) )
+
+#define S32_1(x) ( (SHR32((x),   1)) ^ \
+	               (SHL32((x),   2)) ^ \
+	               (ROTL32((x),  8)) ^ \
+	               (ROTR32((x),  9)) )
+
+#define S32_2(x) ( (SHR32((x),   2)) ^ \
+	               (SHL32((x),   1)) ^ \
+	               (ROTL32((x), 12)) ^ \
+	               (ROTR32((x),  7)) )
+
+#define S32_3(x) ( (SHR32((x),   2)) ^ \
+	               (SHL32((x),   2)) ^ \
+	               (ROTL32((x), 15)) ^ \
+	               (ROTR32((x),  3)) )
+
+#define S32_4(x) ( (SHR32((x),   1)) ^ (x))
+
+#define S32_5(x) ( (SHR32((x),   2)) ^ (x))
+/*
+uint32_t s32_0(uint32_t x){
+	return S32_0(x);
+}
+
+uint32_t s32_1(uint32_t x){
+	return S32_1(x);
+}
+
+uint32_t s32_2(uint32_t x){
+	return S32_2(x);
+}
+
+uint32_t s32_3(uint32_t x){
+	return S32_3(x);
+}
+
+uint32_t s32_4(uint32_t x){
+	return S32_4(x);
+}
+
+uint32_t s32_5(uint32_t x){
+	return S32_5(x);
+}
+*/
+
+ uint32_t bmw_s32_0(uint32_t);
+ uint32_t bmw_s32_1(uint32_t);
+ uint32_t bmw_s32_2(uint32_t);
+ uint32_t bmw_s32_3(uint32_t);
+ uint32_t bmw_s32_4(uint32_t);
+ uint32_t bmw_s32_5(uint32_t);
+ void bmw_small_f0(uint32_t* q, uint32_t* h, const uint32_t* m);
+
+#define R32_1(x)   (ROTL32((x),  3))
+#define R32_2(x)   (ROTL32((x),  7))
+#define R32_3(x)   (ROTL32((x), 13))
+#define R32_4(x)   (ROTL32((x), 16))
+#define R32_5(x)   (ROTR32((x), 13))
+#define R32_6(x)   (ROTR32((x),  9))
+#define R32_7(x)   (ROTR32((x),  5))
+/*
+#define K 0x05555555L
+static
+uint32_t k_lut[] PROGMEM = {
+	16L*K, 17L*K, 18L*K, 19L*K, 20L*K, 21L*K, 22L*K, 23L*K,
+	24L*K, 25L*K, 26L*K, 27L*K, 28L*K, 29L*K, 30L*K, 31L*K
+};
+*/
+/* same as above but precomputed to avoid compiler warnings */
+
+static
+uint32_t k_lut[] = {
+	0x55555550L, 0x5aaaaaa5L, 0x5ffffffaL,
+	0x6555554fL, 0x6aaaaaa4L, 0x6ffffff9L,
+	0x7555554eL, 0x7aaaaaa3L, 0x7ffffff8L,
+	0x8555554dL, 0x8aaaaaa2L, 0x8ffffff7L,
+	0x9555554cL, 0x9aaaaaa1L, 0x9ffffff6L,
+	0xa555554bL };
+
+static
+uint32_t bmw_small_expand1(uint8_t j, const uint32_t* q, const void* m, const void* h){
+	uint32_t r;
+	/* r = 0x05555555*(j+16); */
+
+	r = (   ROTL32(((uint32_t*)m)[j&0xf],      ((j+0)&0xf)+1  )
+	       + ROTL32(((uint32_t*)m)[(j+3)&0xf],  ((j+3)&0xf)+1  )
+	       - ROTL32(((uint32_t*)m)[(j+10)&0xf], ((j+10)&0xf)+1 )
+	       + k_lut[j]
+	     ) ^ ((uint32_t*)h)[(j+7)&0xf];
+	r += bmw_s32_1(q[j+ 0]) + bmw_s32_2(q[j+ 1]) + bmw_s32_3(q[j+ 2]) + bmw_s32_0(q[j+ 3])
+       + bmw_s32_1(q[j+ 4]) + bmw_s32_2(q[j+ 5]) + bmw_s32_3(q[j+ 6]) + bmw_s32_0(q[j+ 7])
+	   + bmw_s32_1(q[j+ 8]) + bmw_s32_2(q[j+ 9]) + bmw_s32_3(q[j+10]) + bmw_s32_0(q[j+11])
+       + bmw_s32_1(q[j+12]) + bmw_s32_2(q[j+13]) + bmw_s32_3(q[j+14]) + bmw_s32_0(q[j+15]);
+	return r;
+}
+
+static
+uint32_t bmw_small_expand2(uint8_t j, const uint32_t* q, const void* m, const void* h){
+	uint32_t r;
+	r  = (   ROTL32(((uint32_t*)m)[j&0xf],      ((j+0)&0xf)+1  )
+	       + ROTL32(((uint32_t*)m)[(j+3)&0xf],  ((j+3)&0xf)+1  )
+	       - ROTL32(((uint32_t*)m)[(j+10)&0xf], ((j+10)&0xf)+1 )
+	       + k_lut[j]
+	     ) ^ ((uint32_t*)h)[(j+7)&0xf];
+	r +=      (q[j+ 0]) + R32_1(q[j+ 1]) +      (q[j+ 2]) + R32_2(q[j+ 3])
+       +      (q[j+ 4]) + R32_3(q[j+ 5]) +      (q[j+ 6]) + R32_4(q[j+ 7])
+	   +      (q[j+ 8]) + R32_5(q[j+ 9]) +      (q[j+10]) + R32_6(q[j+11])
+       +      (q[j+12]) + R32_7(q[j+13]) + S32_4(q[j+14]) + S32_5(q[j+15]);
+	return r;
+}
+
+#if F0_HACK==2
+/* to understand this implementation take a look at f0-opt-table.txt */
+static uint16_t hack_table[5] = { 0x0311, 0xDDB3, 0x2A79, 0x07AA, 0x51C2 };
+static uint8_t  offset_table[5] = { 4+16, 6+16, 9+16, 12+16, 13+16 };
+
+static
+void bmw_small_f0(uint32_t* q, uint32_t* h, const void* m){
+	uint16_t hack_reg;
+	uint8_t c,i,j;
+	uint32_t(*s[])(uint32_t)={ bmw_small_s0, bmw_small_s1, bmw_small_s2,
+	                           bmw_small_s3, bmw_small_s4 };
+	for(i=0; i<16; ++i){
+		((uint32_t*)h)[i] ^= ((uint32_t*)m)[i];
+	}
+	dump_x(h, 16, 'T');
+	memset(q, 0, 4*16);
+	c=4;
+	do{
+		i=15;
+		j=offset_table[c];
+		hack_reg=hack_table[c];
+		do{
+			if(hack_reg&1){
+				q[i]-= h[j&15];
+			}else{
+				q[i]+= h[j&15];
+			}
+			--j;
+			hack_reg>>= 1;
+		}while(i--!=0);
+	}while(c--!=0);
+	dump_x(q, 16, 'W');
+	for(i=0; i<16; ++i){
+		q[i] = s[i%5](q[i]);
+	}
+	for(i=0; i<16; ++i){
+		((uint32_t*)h)[i] ^= ((uint32_t*)m)[i];
+	}
+	for(i=0; i<16; ++i){
+		q[i] += h[(i+1)&0xf];
+	}
+}
+#endif /* F0_HACK==2*/
+
+#if F0_HACK==1
+static
+uint8_t f0_lut[] PROGMEM = {
+	 5<<1, ( 7<<1)+1, (10<<1)+0, (13<<1)+0, (14<<1)+0,
+	 6<<1, ( 8<<1)+1, (11<<1)+0, (14<<1)+0, (15<<1)+1,
+	 0<<1, ( 7<<1)+0, ( 9<<1)+0, (12<<1)+1, (15<<1)+0,
+	 0<<1, ( 1<<1)+1, ( 8<<1)+0, (10<<1)+1, (13<<1)+0,
+	 1<<1, ( 2<<1)+0, ( 9<<1)+0, (11<<1)+1, (14<<1)+1,
+	 3<<1, ( 2<<1)+1, (10<<1)+0, (12<<1)+1, (15<<1)+0,
+	 4<<1, ( 0<<1)+1, ( 3<<1)+1, (11<<1)+1, (13<<1)+0,
+	 1<<1, ( 4<<1)+1, ( 5<<1)+1, (12<<1)+1, (14<<1)+1,
+	 2<<1, ( 5<<1)+1, ( 6<<1)+1, (13<<1)+0, (15<<1)+1,
+	 0<<1, ( 3<<1)+1, ( 6<<1)+0, ( 7<<1)+1, (14<<1)+0,
+	 8<<1, ( 1<<1)+1, ( 4<<1)+1, ( 7<<1)+1, (15<<1)+0,
+	 8<<1, ( 0<<1)+1, ( 2<<1)+1, ( 5<<1)+1, ( 9<<1)+0,
+	 1<<1, ( 3<<1)+0, ( 6<<1)+1, ( 9<<1)+1, (10<<1)+0,
+	 2<<1, ( 4<<1)+0, ( 7<<1)+0, (10<<1)+0, (11<<1)+0,
+	 3<<1, ( 5<<1)+1, ( 8<<1)+0, (11<<1)+1, (12<<1)+1,
+	12<<1, ( 4<<1)+1, ( 6<<1)+1, ( 9<<1)+1, (13<<1)+0
+};
+
+static
+void bmw_small_f0(uint32_t* q, uint32_t* h, const void* m){
+	uint8_t i,j=-1,v,sign,l=0;
+	uint32_t(*s[])(uint32_t)={ bmw_small_s0, bmw_small_s1, bmw_small_s2,
+	                           bmw_small_s3, bmw_small_s4 };
+	for(i=0; i<16; ++i){
+		((uint32_t*)h)[i] ^= ((uint32_t*)m)[i];
+	}
+	dump_x(h, 16, 'T');
+	// memset(q, 0, 4*16);
+	for(i=0; i<5*16; ++i){
+		v = pgm_read_byte(f0_lut+i);
+		sign = v&1;
+		v >>=1;
+		if(i==l){
+			j++;
+			l+=5;
+			q[j] = h[v];
+			continue;
+		}
+		if(sign){
+			q[j] -= h[v];
+		}else{
+			q[j] += h[v];
+		}
+	}
+	dump_x(q, 16, 'W');
+	for(i=0; i<16; ++i){
+		q[i] = s[i%5](q[i]);
+	}
+	for(i=0; i<16; ++i){
+		((uint32_t*)h)[i] ^= ((uint32_t*)m)[i];
+	}
+	for(i=0; i<16; ++i){
+		q[i] += h[(i+1)&0xf];
+	}
+}
+#endif /* F0_HACK==1 */
+
+#if F0_HACK==0
+/*
+static
+void bmw_small_f0(uint32_t* q, uint32_t* h, const void* m){
+	uint8_t i;
+	for(i=0; i<16; ++i){
+		((uint32_t*)h)[i] ^= ((uint32_t*)m)[i];
+	}
+	dump_x(h, 16, 'T');
+	q[ 0] = (h[ 5] - h[ 7] + h[10] + h[13] + h[14]);
+	q[ 1] = (h[ 6] - h[ 8] + h[11] + h[14] - h[15]);
+	q[ 2] = (h[ 0] + h[ 7] + h[ 9] - h[12] + h[15]);
+	q[ 3] = (h[ 0] - h[ 1] + h[ 8] - h[10] + h[13]);
+	q[ 4] = (h[ 1] + h[ 2] + h[ 9] - h[11] - h[14]);
+	q[ 5] = (h[ 3] - h[ 2] + h[10] - h[12] + h[15]);
+	q[ 6] = (h[ 4] - h[ 0] - h[ 3] - h[11] + h[13]);
+	q[ 7] = (h[ 1] - h[ 4] - h[ 5] - h[12] - h[14]);
+	q[ 8] = (h[ 2] - h[ 5] - h[ 6] + h[13] - h[15]);
+	q[ 9] = (h[ 0] - h[ 3] + h[ 6] - h[ 7] + h[14]);
+	q[10] = (h[ 8] - h[ 1] - h[ 4] - h[ 7] + h[15]);
+	q[11] = (h[ 8] - h[ 0] - h[ 2] - h[ 5] + h[ 9]);
+	q[12] = (h[ 1] + h[ 3] - h[ 6] - h[ 9] + h[10]);
+	q[13] = (h[ 2] + h[ 4] + h[ 7] + h[10] + h[11]);
+	q[14] = (h[ 3] - h[ 5] + h[ 8] - h[11] - h[12]);
+	q[15] = (h[12] - h[ 4] - h[ 6] - h[ 9] + h[13]);
+	dump_x(q, 16, 'W');
+    q[ 0] = bmw_s32_0(q[ 0]);
+    q[ 1] = bmw_s32_1(q[ 1]);
+    q[ 2] = bmw_s32_2(q[ 2]);
+    q[ 3] = bmw_s32_3(q[ 3]);
+    q[ 4] = bmw_s32_4(q[ 4]);
+    q[ 5] = bmw_s32_0(q[ 5]);
+    q[ 6] = bmw_s32_1(q[ 6]);
+    q[ 7] = bmw_s32_2(q[ 7]);
+    q[ 8] = bmw_s32_3(q[ 8]);
+    q[ 9] = bmw_s32_4(q[ 9]);
+    q[10] = bmw_s32_0(q[10]);
+    q[11] = bmw_s32_1(q[11]);
+    q[12] = bmw_s32_2(q[12]);
+    q[13] = bmw_s32_3(q[13]);
+    q[14] = bmw_s32_4(q[14]);
+    q[15] = bmw_s32_0(q[15]);
+	for(i=0; i<16; ++i){
+		((uint32_t*)h)[i] ^= ((uint32_t*)m)[i];
+	}
+	for(i=0; i<16; ++i){
+		q[i] += h[(i+1)&0xf];
+	}
+}
+*/
+#endif /* F0_HACK==0 */
+
+static
+void bmw_small_f1(uint32_t* q, const void* m, const void* h){
+	uint8_t i;
+	q[16] = bmw_small_expand1(0, q, m, h);
+	q[17] = bmw_small_expand1(1, q, m, h);
+	for(i=2; i<16; ++i){
+		q[16+i] = bmw_small_expand2(i, q, m, h);
+	}
+}
+
+static
+void bmw_small_f2(uint32_t* h, uint32_t* q, const void* m){
+	uint32_t xl=0, xh;
+	uint8_t i;
+	for(i=16;i<24;++i){
+		xl ^= q[i];
+	}
+	xh = xl;
+	for(i=24;i<32;++i){
+		xh ^= q[i];
+	}
+#if DEBUG
+	cli_putstr("\r\n XL = ");
+	cli_hexdump_rev(&xl, 4);
+	cli_putstr("\r\n XH = ");
+	cli_hexdump_rev(&xh, 4);
+#endif
+	memcpy(h, m, 16*4);
+	h[0] ^= SHL32(xh, 5) ^ SHR32(q[16], 5);
+	h[1] ^= SHR32(xh, 7) ^ SHL32(q[17], 8);
+	h[2] ^= SHR32(xh, 5) ^ SHL32(q[18], 5);
+	h[3] ^= SHR32(xh, 1) ^ SHL32(q[19], 5);
+	h[4] ^= SHR32(xh, 3) ^ q[20];
+	h[5] ^= SHL32(xh, 6) ^ SHR32(q[21], 6);
+	h[6] ^= SHR32(xh, 4) ^ SHL32(q[22], 6);
+	h[7] ^= SHR32(xh,11) ^ SHL32(q[23], 2);
+	for(i=0; i<8; ++i){
+		h[i] += xl ^ q[24+i] ^ q[i];
+	}
+	for(i=0; i<8; ++i){
+		h[8+i] ^= xh ^ q[24+i];
+		h[8+i] += ROTL32(h[(4+i)%8],i+9);
+	}
+/*
+	h[ 8] += SHL32(xl, 8) ^ q[23] ^ q[ 8];
+	h[ 9] += SHR32(xl, 6) ^ q[16] ^ q[ 9];
+	h[10] += SHL32(xl, 6) ^ q[17] ^ q[10];
+	h[11] += SHL32(xl, 4) ^ q[18] ^ q[11];
+	h[12] += SHR32(xl, 3) ^ q[19] ^ q[12];
+	h[13] += SHR32(xl, 4) ^ q[20] ^ q[13];
+	h[14] += SHR32(xl, 7) ^ q[21] ^ q[14];
+	h[15] += SHR32(xl, 2) ^ q[22] ^ q[15];
+*/
+	memxor(q+9, q+16, 7*4);
+	q[8] ^= q[23];
+	h[ 8] += SHL32(xl, 8) ^ q[ 8];
+	h[ 9] += SHR32(xl, 6) ^ q[ 9];
+	h[10] += SHL32(xl, 6) ^ q[10];
+	h[11] += SHL32(xl, 4) ^ q[11];
+	h[12] += SHR32(xl, 3) ^ q[12];
+	h[13] += SHR32(xl, 4) ^ q[13];
+	h[14] += SHR32(xl, 7) ^ q[14];
+	h[15] += SHR32(xl, 2) ^ q[15];
+
+}
+
+void bmw_small_nextBlock(bmw_small_ctx_t* ctx, const void* block){
+	uint32_t q[32];
+	dump_x(block, 16, 'M');
+	bmw_small_f0(q, ctx->h, block);
+	dump_x(q, 16, 'Q');
+	bmw_small_f1(q, block, ctx->h);
+	dump_x(q, 32, 'Q');
+	bmw_small_f2(ctx->h, q, block);
+	ctx->counter += 1;
+	ctx_dump(ctx);
+}
+
+void bmw_small_lastBlock(bmw_small_ctx_t* ctx, const void* block, uint16_t length_b){
+	uint8_t buffer[64];
+	while(length_b >= BMW_SMALL_BLOCKSIZE){
+		bmw_small_nextBlock(ctx, block);
+		length_b -= BMW_SMALL_BLOCKSIZE;
+		block = (uint8_t*)block + BMW_SMALL_BLOCKSIZE_B;
+	}
+	memset(buffer, 0, 64);
+	memcpy(buffer, block, (length_b+7)/8);
+	buffer[length_b>>3] |= 0x80 >> (length_b&0x07);
+	if(length_b+1>64*8-64){
+		bmw_small_nextBlock(ctx, buffer);
+		memset(buffer, 0, 64-8);
+		ctx->counter -= 1;
+	}
+	*((uint64_t*)&(buffer[64-8])) = (uint64_t)(ctx->counter*512LL)+(uint64_t)length_b;
+	bmw_small_nextBlock(ctx, buffer);
+#if TWEAK
+	uint8_t i;
+	uint32_t q[32];
+	memset(buffer, 0xaa, 64);
+	for(i=0; i<16;++i){
+		buffer[i*4] = i+0xa0;
+	}
+//	dump_x(buffer, 16, 'A');
+	dump_x(ctx->h, 16, 'M');
+	bmw_small_f0(q, (uint32_t*)buffer, ctx->h);
+	dump_x(buffer, 16, 'a');
+	dump_x(q, 16, 'Q');
+	bmw_small_f1(q, ctx->h, (uint32_t*)buffer);
+	dump_x(q, 32, 'Q');
+	bmw_small_f2((uint32_t*)buffer, q, ctx->h);
+	memcpy(ctx->h, buffer, 64);
+#endif
+}
+
+void bmw224_init(bmw224_ctx_t* ctx){
+	uint8_t i;
+	ctx->h[0] = 0x00010203;
+	for(i=1; i<16; ++i){
+		ctx->h[i] = ctx->h[i-1]+ 0x04040404;
+	}
+#if BUG24
+	ctx->h[13] = 0x24353637;
+#endif
+	ctx->counter=0;
+	ctx_dump(ctx);
+}
+
+void bmw256_init(bmw256_ctx_t* ctx){
+	uint8_t i;
+	ctx->h[0] = 0x40414243;
+	for(i=1; i<16; ++i){
+		ctx->h[i] = ctx->h[i-1]+ 0x04040404;
+	}
+	ctx->counter=0;
+	ctx_dump(ctx);
+}
+
+void bmw224_nextBlock(bmw224_ctx_t* ctx, const void* block){
+	bmw_small_nextBlock(ctx, block);
+}
+
+void bmw256_nextBlock(bmw256_ctx_t* ctx, const void* block){
+	bmw_small_nextBlock(ctx, block);
+}
+
+void bmw224_lastBlock(bmw224_ctx_t* ctx, const void* block, uint16_t length_b){
+	bmw_small_lastBlock(ctx, block, length_b);
+}
+
+void bmw256_lastBlock(bmw256_ctx_t* ctx, const void* block, uint16_t length_b){
+	bmw_small_lastBlock(ctx, block, length_b);
+}
+
+void bmw224_ctx2hash(void* dest, const bmw224_ctx_t* ctx){
+	memcpy(dest, &(ctx->h[9]), 224/8);
+}
+
+void bmw256_ctx2hash(void* dest, const bmw256_ctx_t* ctx){
+	memcpy(dest, &(ctx->h[8]), 256/8);
+}
+
+void bmw224(void* dest, const void* msg, uint32_t length_b){
+	bmw_small_ctx_t ctx;
+	bmw224_init(&ctx);
+	while(length_b>=BMW_SMALL_BLOCKSIZE){
+		bmw_small_nextBlock(&ctx, msg);
+		length_b -= BMW_SMALL_BLOCKSIZE;
+		msg = (uint8_t*)msg + BMW_SMALL_BLOCKSIZE_B;
+	}
+	bmw_small_lastBlock(&ctx, msg, length_b);
+	bmw224_ctx2hash(dest, &ctx);
+}
+
+void bmw256(void* dest, const void* msg, uint32_t length_b){
+	bmw_small_ctx_t ctx;
+	bmw256_init(&ctx);
+	while(length_b>=BMW_SMALL_BLOCKSIZE){
+		bmw_small_nextBlock(&ctx, msg);
+		length_b -= BMW_SMALL_BLOCKSIZE;
+		msg = (uint8_t*)msg + BMW_SMALL_BLOCKSIZE_B;
+	}
+	bmw_small_lastBlock(&ctx, msg, length_b);
+	bmw256_ctx2hash(dest, &ctx);
+}
+
diff --git a/bmw/bmw_small-asm-cstub.s b/bmw/bmw_small-asm-cstub.s
new file mode 100644
index 0000000..64ea49b
--- /dev/null
+++ b/bmw/bmw_small-asm-cstub.s
@@ -0,0 +1,1275 @@
+	.syntax unified
+	.thumb
+	.file	"bmw_small-asm-cstub.c"
+	.text
+	.align	2
+	.global	s32_0
+	.thumb
+	.thumb_func
+	.type	s32_0, %function
+s32_0:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r3, r0
+	lsrs	r0, r0, #1
+	eor	r0, r0, r3, lsl #3
+	eor	r0, r0, r3, ror #28
+	eor	r0, r0, r3, ror #13
+	bx	lr
+	.size	s32_0, .-s32_0
+	.align	2
+	.global	s32_1
+	.thumb
+	.thumb_func
+	.type	s32_1, %function
+s32_1:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r3, r0
+	lsrs	r0, r0, #1
+	eor	r0, r0, r3, lsl #2
+	eor	r0, r0, r3, ror #24
+	eor	r0, r0, r3, ror #9
+	bx	lr
+	.size	s32_1, .-s32_1
+	.align	2
+	.global	s32_2
+	.thumb
+	.thumb_func
+	.type	s32_2, %function
+s32_2:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r3, r0
+	lsrs	r0, r0, #2
+	eor	r0, r0, r3, lsl #1
+	eor	r0, r0, r3, ror #20
+	eor	r0, r0, r3, ror #7
+	bx	lr
+	.size	s32_2, .-s32_2
+	.align	2
+	.global	s32_3
+	.thumb
+	.thumb_func
+	.type	s32_3, %function
+s32_3:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r3, r0
+	lsrs	r0, r0, #2
+	eor	r0, r0, r3, lsl #2
+	eor	r0, r0, r3, ror #17
+	eor	r0, r0, r3, ror #3
+	bx	lr
+	.size	s32_3, .-s32_3
+	.align	2
+	.global	s32_4
+	.thumb
+	.thumb_func
+	.type	s32_4, %function
+s32_4:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	eor	r0, r0, r0, lsr #1
+	bx	lr
+	.size	s32_4, .-s32_4
+	.align	2
+	.global	s32_5
+	.thumb
+	.thumb_func
+	.type	s32_5, %function
+s32_5:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	eor	r0, r0, r0, lsr #2
+	bx	lr
+	.size	s32_5, .-s32_5
+	.align	2
+	.thumb
+	.thumb_func
+	.type	bmw_small_expand1, %function
+bmw_small_expand1:
+	@ args = 0, pretend = 0, frame = 32
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	uxtb	r0, r0
+	and	ip, r0, #15
+	push	{r4, r5, r6, r7, r8, r9, sl, fp}
+	ldr	r4, [r2, ip, lsl #2]
+	mvn	sl, ip
+	add	sl, sl, #32
+	add	ip, ip, #1
+	lsr	sl, r4, sl
+	lsl	r4, r4, ip
+	add	fp, r0, #3
+	add	r7, r0, #10
+	and	r5, fp, #15
+	and	r8, r7, #15
+	ldr	r6, [r2, r5, lsl #2]
+	ldr	r9, [r2, r8, lsl #2]
+	ldr	r2, .L15
+	orr	sl, sl, r4
+	ldr	ip, [r2, r0, lsl #2]
+	mvn	r2, r5
+	add	sl, sl, ip
+	adds	r5, r5, #1
+	adds	r2, r2, #32
+	mvn	ip, r8
+	lsrs	r2, r6, r2
+	add	r8, r8, #1
+	lsls	r6, r6, r5
+	add	ip, ip, #32
+	lsr	ip, r9, ip
+	lsl	r9, r9, r8
+	sub	sp, sp, #32
+	orrs	r2, r2, r6
+	str	r7, [sp, #0]
+	adds	r7, r0, #7
+	orr	ip, ip, r9
+	add	sl, sl, r2
+	and	r2, r7, #15
+	rsb	sl, ip, sl
+	ldr	ip, [r3, r2, lsl #2]
+	adds	r2, r0, #2
+	ldr	r4, [r1, r2, lsl #2]
+	adds	r3, r0, #1
+	adds	r2, r0, #5
+	ldr	r9, [r1, r2, lsl #2]
+	eor	sl, sl, ip
+	add	r2, r0, #9
+	ldr	ip, [r1, r3, lsl #2]
+	adds	r3, r0, #4
+	ldr	r8, [r1, r3, lsl #2]
+	ldr	r2, [r1, r2, lsl #2]
+	adds	r3, r0, #6
+	ldr	r6, [r1, fp, lsl #2]
+	ldr	fp, [r1, r3, lsl #2]
+	add	r3, r0, #8
+	ldr	r3, [r1, r3, lsl #2]
+	str	r2, [sp, #8]
+	ldr	r2, [sp, #0]
+	str	r3, [sp, #4]
+	ldr	r2, [r1, r2, lsl #2]
+	add	r3, r0, #11
+	ldr	r3, [r1, r3, lsl #2]
+	str	r2, [sp, #12]
+	add	r2, r0, #12
+	ldr	r2, [r1, r2, lsl #2]
+	str	r3, [sp, #16]
+	add	r3, r0, #13
+	ldr	r3, [r1, r3, lsl #2]
+	ldr	r5, [r1, r0, lsl #2]
+	str	r2, [sp, #20]
+	add	r2, r0, #14
+	adds	r0, r0, #15
+	ldr	r7, [r1, r7, lsl #2]
+	ldr	r2, [r1, r2, lsl #2]
+	str	r3, [sp, #24]
+	ldr	r1, [r1, r0, lsl #2]
+	lsrs	r3, r4, #2
+	lsr	r0, ip, #2
+	eor	r0, r0, ip, lsl #1
+	eor	r3, r3, r4, lsl #2
+	eor	r0, r0, ip, ror #20
+	eor	r3, r3, r4, ror #17
+	str	r2, [sp, #28]
+	eor	r3, r3, r4, ror #3
+	lsrs	r2, r5, #1
+	eor	r0, r0, ip, ror #7
+	adds	r0, r0, r3
+	eor	r2, r2, r5, lsl #2
+	lsrs	r3, r6, #1
+	eor	r2, r2, r5, ror #24
+	eor	r3, r3, r6, lsl #3
+	eor	r2, r2, r5, ror #9
+	eor	r3, r3, r6, ror #28
+	adds	r0, r0, r2
+	eor	r3, r3, r6, ror #13
+	lsr	r2, r8, #1
+	adds	r0, r0, r3
+	eor	r2, r2, r8, lsl #2
+	lsr	r3, r9, #2
+	eor	r2, r2, r8, ror #24
+	eor	r3, r3, r9, lsl #1
+	eor	r2, r2, r8, ror #9
+	eor	r3, r3, r9, ror #20
+	adds	r0, r0, r2
+	eor	r3, r3, r9, ror #7
+	lsr	r2, fp, #2
+	adds	r0, r0, r3
+	eor	r2, r2, fp, lsl #2
+	lsrs	r3, r7, #1
+	eor	r2, r2, fp, ror #17
+	eor	r3, r3, r7, lsl #3
+	eor	r2, r2, fp, ror #3
+	eor	r3, r3, r7, ror #28
+	adds	r0, r0, r2
+	eor	r3, r3, r7, ror #13
+	adds	r0, r0, r3
+	ldr	r3, [sp, #4]
+	ldr	r7, [sp, #8]
+	lsrs	r2, r3, #1
+	eor	r2, r2, r3, lsl #2
+	eor	r2, r2, r3, ror #24
+	eor	r2, r2, r3, ror #9
+	lsrs	r3, r7, #2
+	eor	r3, r3, r7, lsl #1
+	eor	r3, r3, r7, ror #20
+	adds	r0, r0, r2
+	eor	r3, r3, r7, ror #7
+	adds	r0, r0, r3
+	ldr	r3, [sp, #12]
+	ldr	r7, [sp, #16]
+	lsrs	r2, r3, #2
+	eor	r2, r2, r3, lsl #2
+	eor	r2, r2, r3, ror #17
+	eor	r2, r2, r3, ror #3
+	lsrs	r3, r7, #1
+	eor	r3, r3, r7, lsl #3
+	eor	r3, r3, r7, ror #28
+	adds	r0, r0, r2
+	eor	r3, r3, r7, ror #13
+	adds	r0, r0, r3
+	ldr	r3, [sp, #20]
+	ldr	r7, [sp, #24]
+	lsrs	r2, r3, #1
+	eor	r2, r2, r3, lsl #2
+	eor	r2, r2, r3, ror #24
+	eor	r2, r2, r3, ror #9
+	adds	r0, r0, r2
+	lsrs	r3, r7, #2
+	eor	r3, r3, r7, lsl #1
+	eor	r3, r3, r7, ror #20
+	eor	r3, r3, r7, ror #7
+	adds	r0, r0, r3
+	ldr	r3, [sp, #28]
+	lsrs	r2, r3, #2
+	eor	r2, r2, r3, lsl #2
+	eor	r2, r2, r3, ror #17
+	eor	r2, r2, r3, ror #3
+	lsrs	r3, r1, #1
+	eor	r3, r3, r1, lsl #3
+	eor	r3, r3, r1, ror #28
+	adds	r0, r0, r2
+	eor	r3, r3, r1, ror #13
+	adds	r0, r0, r3
+	add	r0, r0, sl
+	add	sp, sp, #32
+	pop	{r4, r5, r6, r7, r8, r9, sl, fp}
+	bx	lr
+.L16:
+	.align	2
+.L15:
+	.word	k_lut
+	.size	bmw_small_expand1, .-bmw_small_expand1
+	.align	2
+	.thumb
+	.thumb_func
+	.type	bmw_small_f0, %function
+bmw_small_f0:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	push	{r4, r5}
+	mov	r5, r0
+	mov	r4, r1
+	mov	r0, r2
+	movs	r1, #0
+.L18:
+	ldr	r3, [r4, r1]
+	ldr	r2, [r0, r1]
+	eors	r3, r3, r2
+	str	r3, [r4, r1]
+	adds	r1, r1, #4
+	cmp	r1, #64
+	bne	.L18
+	ldr	r2, [r4, #20]
+	ldr	r3, [r4, #40]
+	ldr	r1, [r4, #52]
+	adds	r3, r3, r2
+	ldr	r2, [r4, #56]
+	adds	r3, r3, r1
+	ldr	r1, [r4, #28]
+	adds	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #0]
+	ldr	r3, [r4, #24]
+	ldr	r2, [r4, #44]
+	ldr	r1, [r4, #56]
+	adds	r2, r2, r3
+	ldr	r3, [r4, #60]
+	adds	r2, r2, r1
+	ldr	r1, [r4, #32]
+	subs	r2, r2, r3
+	subs	r2, r2, r1
+	str	r2, [r5, #4]
+	ldr	r2, [r4, #36]
+	ldr	r3, [r4, #28]
+	ldr	r1, [r4, #0]
+	adds	r3, r3, r2
+	ldr	r2, [r4, #60]
+	adds	r3, r3, r1
+	ldr	r1, [r4, #48]
+	adds	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #8]
+	ldr	r3, [r4, #52]
+	ldr	r2, [r4, #32]
+	ldr	r1, [r4, #0]
+	adds	r2, r2, r3
+	ldr	r3, [r4, #4]
+	adds	r2, r2, r1
+	ldr	r1, [r4, #40]
+	subs	r2, r2, r3
+	subs	r2, r2, r1
+	str	r2, [r5, #12]
+	ldr	r2, [r4, #4]
+	ldr	r3, [r4, #8]
+	ldr	r1, [r4, #36]
+	adds	r3, r3, r2
+	ldr	r2, [r4, #56]
+	adds	r3, r3, r1
+	ldr	r1, [r4, #44]
+	subs	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #16]
+	ldr	r3, [r4, #12]
+	ldr	r2, [r4, #40]
+	ldr	r1, [r4, #60]
+	adds	r2, r2, r3
+	ldr	r3, [r4, #8]
+	adds	r2, r2, r1
+	ldr	r1, [r4, #48]
+	subs	r2, r2, r3
+	subs	r2, r2, r1
+	str	r2, [r5, #20]
+	ldr	r2, [r4, #0]
+	ldr	r3, [r4, #16]
+	ldr	r1, [r4, #44]
+	subs	r3, r3, r2
+	ldr	r2, [r4, #52]
+	subs	r3, r3, r1
+	ldr	r1, [r4, #12]
+	adds	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #24]
+	ldr	r3, [r4, #16]
+	ldr	r2, [r4, #4]
+	ldr	r1, [r4, #20]
+	subs	r2, r2, r3
+	ldr	r3, [r4, #48]
+	subs	r2, r2, r1
+	ldr	r1, [r4, #56]
+	subs	r2, r2, r3
+	subs	r2, r2, r1
+	str	r2, [r5, #28]
+	ldr	r2, [r4, #20]
+	ldr	r3, [r4, #8]
+	ldr	r1, [r4, #60]
+	subs	r3, r3, r2
+	ldr	r2, [r4, #52]
+	subs	r3, r3, r1
+	ldr	r1, [r4, #24]
+	adds	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #32]
+	ldr	r3, [r4, #56]
+	ldr	r2, [r4, #24]
+	ldr	r1, [r4, #0]
+	adds	r2, r2, r3
+	ldr	r3, [r4, #12]
+	adds	r2, r2, r1
+	ldr	r1, [r4, #28]
+	subs	r2, r2, r3
+	subs	r2, r2, r1
+	str	r2, [r5, #36]
+	ldr	r2, [r4, #4]
+	ldr	r3, [r4, #32]
+	ldr	r1, [r4, #28]
+	subs	r3, r3, r2
+	ldr	r2, [r4, #60]
+	subs	r3, r3, r1
+	ldr	r1, [r4, #16]
+	adds	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #40]
+	ldr	r3, [r4, #0]
+	ldr	r2, [r4, #32]
+	ldr	r1, [r4, #20]
+	subs	r2, r2, r3
+	ldr	r3, [r4, #36]
+	subs	r2, r2, r1
+	ldr	r1, [r4, #8]
+	adds	r2, r2, r3
+	subs	r2, r2, r1
+	str	r2, [r5, #44]
+	ldr	r2, [r4, #4]
+	ldr	r3, [r4, #12]
+	ldr	r1, [r4, #40]
+	adds	r3, r3, r2
+	ldr	r2, [r4, #36]
+	adds	r3, r3, r1
+	ldr	r1, [r4, #24]
+	subs	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #48]
+	ldr	r3, [r4, #8]
+	ldr	r2, [r4, #16]
+	ldr	r1, [r4, #28]
+	adds	r2, r2, r3
+	ldr	r3, [r4, #40]
+	adds	r2, r2, r1
+	ldr	r1, [r4, #44]
+	adds	r2, r2, r3
+	adds	r2, r2, r1
+	str	r2, [r5, #52]
+	ldr	r2, [r4, #12]
+	ldr	r3, [r4, #32]
+	ldr	r1, [r4, #48]
+	adds	r3, r3, r2
+	ldr	r2, [r4, #44]
+	subs	r3, r3, r1
+	ldr	r1, [r4, #20]
+	subs	r3, r3, r2
+	subs	r3, r3, r1
+	str	r3, [r5, #56]
+	ldr	r2, [r4, #36]
+	ldr	r3, [r4, #24]
+	ldr	r1, [r4, #52]
+	rsb	r2, r2, #0
+	subs	r2, r2, r3
+	adds	r2, r2, r1
+	ldr	r3, [r4, #48]
+	ldr	r1, [r4, #16]
+	subs	r3, r3, r1
+	ldr	r1, [r5, #0]
+	adds	r2, r2, r3
+	lsrs	r3, r1, #1
+	eor	r3, r3, r1, lsl #3
+	str	r2, [r5, #60]
+	eor	r3, r3, r1, ror #28
+	ldr	r2, [r5, #4]
+	eor	r3, r3, r1, ror #13
+	str	r3, [r5, #0]
+	lsrs	r3, r2, #1
+	eor	r3, r3, r2, lsl #2
+	eor	r3, r3, r2, ror #24
+	eor	r3, r3, r2, ror #9
+	ldr	r2, [r5, #8]
+	str	r3, [r5, #4]
+	lsrs	r3, r2, #2
+	eor	r3, r3, r2, lsl #1
+	eor	r3, r3, r2, ror #20
+	eor	r3, r3, r2, ror #7
+	ldr	r2, [r5, #12]
+	str	r3, [r5, #8]
+	lsrs	r3, r2, #2
+	eor	r3, r3, r2, lsl #2
+	eor	r3, r3, r2, ror #17
+	eor	r3, r3, r2, ror #3
+	ldr	r2, [r5, #16]
+	str	r3, [r5, #12]
+	eor	r2, r2, r2, lsr #1
+	str	r2, [r5, #16]
+	ldr	r1, [r5, #20]
+	ldr	r2, [r5, #24]
+	lsrs	r3, r1, #1
+	eor	r3, r3, r1, lsl #3
+	eor	r3, r3, r1, ror #28
+	eor	r3, r3, r1, ror #13
+	str	r3, [r5, #20]
+	lsrs	r3, r2, #1
+	eor	r3, r3, r2, lsl #2
+	eor	r3, r3, r2, ror #24
+	eor	r3, r3, r2, ror #9
+	ldr	r2, [r5, #28]
+	str	r3, [r5, #24]
+	lsrs	r3, r2, #2
+	eor	r3, r3, r2, lsl #1
+	eor	r3, r3, r2, ror #20
+	eor	r3, r3, r2, ror #7
+	ldr	r2, [r5, #32]
+	str	r3, [r5, #28]
+	lsrs	r3, r2, #2
+	eor	r3, r3, r2, lsl #2
+	ldr	r1, [r5, #40]
+	eor	r3, r3, r2, ror #17
+	eor	r3, r3, r2, ror #3
+	ldr	r2, [r5, #36]
+	str	r3, [r5, #32]
+	lsrs	r3, r1, #1
+	eor	r2, r2, r2, lsr #1
+	eor	r3, r3, r1, lsl #3
+	eor	r3, r3, r1, ror #28
+	str	r2, [r5, #36]
+	ldr	r2, [r5, #44]
+	eor	r3, r3, r1, ror #13
+	str	r3, [r5, #40]
+	lsrs	r3, r2, #1
+	eor	r3, r3, r2, lsl #2
+	eor	r3, r3, r2, ror #24
+	eor	r3, r3, r2, ror #9
+	ldr	r2, [r5, #48]
+	str	r3, [r5, #44]
+	lsrs	r3, r2, #2
+	eor	r3, r3, r2, lsl #1
+	eor	r3, r3, r2, ror #20
+	eor	r3, r3, r2, ror #7
+	ldr	r2, [r5, #52]
+	str	r3, [r5, #48]
+	lsrs	r3, r2, #2
+	eor	r3, r3, r2, lsl #2
+	ldr	r1, [r5, #60]
+	eor	r3, r3, r2, ror #17
+	eor	r3, r3, r2, ror #3
+	str	r3, [r5, #52]
+	lsrs	r3, r1, #1
+	ldr	r2, [r5, #56]
+	eor	r3, r3, r1, lsl #3
+	eor	r3, r3, r1, ror #28
+	eor	r3, r3, r1, ror #13
+	eor	r2, r2, r2, lsr #1
+	str	r2, [r5, #56]
+	str	r3, [r5, #60]
+	movs	r1, #0
+.L19:
+	ldr	r3, [r4, r1]
+	ldr	r2, [r0, r1]
+	eors	r3, r3, r2
+	str	r3, [r4, r1]
+	adds	r1, r1, #4
+	cmp	r1, #64
+	bne	.L19
+	mov	ip, #0
+	movs	r0, #1
+.L20:
+	and	r3, r0, #15
+	ldr	r2, [r5, ip]
+	ldr	r1, [r4, r3, lsl #2]
+	adds	r0, r0, #1
+	adds	r2, r2, r1
+	str	r2, [r5, ip]
+	add	ip, ip, #4
+	cmp	ip, #64
+	bne	.L20
+	pop	{r4, r5}
+	bx	lr
+	.size	bmw_small_f0, .-bmw_small_f0
+	.align	2
+	.thumb
+	.thumb_func
+	.type	bmw_small_f1, %function
+bmw_small_f1:
+	@ args = 0, pretend = 0, frame = 4
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{r4, r5, r6, r7, r8, r9, sl, fp, lr}
+	sub	sp, sp, #4
+	mov	r4, r0
+	mov	fp, r1
+	str	r2, [sp, #0]
+	mov	r1, r4
+	mov	r2, fp
+	ldr	r3, [sp, #0]
+	movs	r0, #0
+	bl	bmw_small_expand1
+	mov	r1, r4
+	str	r0, [r4, #64]
+	mov	r2, fp
+	movs	r0, #1
+	ldr	r3, [sp, #0]
+	bl	bmw_small_expand1
+	ldr	r9, .L30
+	str	r0, [r4, #68]
+	mov	lr, r4
+	movs	r6, #0
+	mov	sl, #2
+	mov	r8, #5
+	movs	r7, #12
+.L27:
+	and	r3, sl, #15
+	ldr	r2, [fp, r3, lsl #2]
+	mvn	r0, r3
+	and	r1, r8, #15
+	adds	r3, r3, #1
+	adds	r0, r0, #32
+	ldr	ip, [fp, r1, lsl #2]
+	lsrs	r0, r2, r0
+	lsls	r2, r2, r3
+	mvn	r3, r1
+	adds	r3, r3, #32
+	adds	r1, r1, #1
+	lsr	r3, ip, r3
+	lsl	ip, ip, r1
+	and	r4, r7, #15
+	orrs	r0, r0, r2
+	orr	r3, r3, ip
+	ldr	r5, [fp, r4, lsl #2]
+	adds	r0, r0, r3
+	mvn	r3, r4
+	adds	r3, r3, #32
+	adds	r4, r4, #1
+	lsrs	r3, r5, r3
+	lsls	r5, r5, r4
+	ldr	r2, [r9, #8]
+	ldr	r1, [sp, #0]
+	adds	r0, r0, r2
+	add	r2, r6, #9
+	orrs	r3, r3, r5
+	and	r2, r2, #15
+	subs	r0, r0, r3
+	ldr	r3, [r1, r2, lsl #2]
+	ldr	r2, [lr, #8]
+	eors	r0, r0, r3
+	ldr	r3, [lr, #16]
+	ldr	r1, [lr, #24]
+	adds	r3, r3, r2
+	ldr	r2, [lr, #32]
+	adds	r3, r3, r1
+	ldr	r1, [lr, #40]
+	adds	r3, r3, r2
+	ldr	r2, [lr, #48]
+	adds	r3, r3, r1
+	ldr	r1, [lr, #56]
+	adds	r3, r3, r2
+	ldr	r2, [lr, #12]
+	adds	r3, r3, r1
+	ldr	r1, [lr, #20]
+	add	r3, r3, r2, ror #29
+	ldr	r2, [lr, #28]
+	add	r3, r3, r1, ror #25
+	ldr	r1, [lr, #36]
+	add	r3, r3, r2, ror #19
+	ldr	r2, [lr, #44]
+	add	r3, r3, r1, ror #16
+	ldr	r1, [lr, #52]
+	ldr	ip, [lr, #64]
+	add	r3, r3, r2, ror #13
+	ldr	r2, [lr, #60]
+	ldr	r4, [lr, #68]
+	add	r3, r3, r1, ror #9
+	add	r3, r3, r2, ror #5
+	eor	ip, ip, ip, lsr #1
+	add	r3, r3, ip
+	eor	r4, r4, r4, lsr #2
+	adds	r3, r3, r4
+	adds	r6, r6, #1
+	adds	r3, r3, r0
+	adds	r7, r7, #1
+	cmp	r6, #14
+	str	r3, [lr, #72]
+	add	sl, sl, #1
+	add	r8, r8, #1
+	add	r9, r9, #4
+	add	lr, lr, #4
+	bne	.L27
+	add	sp, sp, #4
+	pop	{r4, r5, r6, r7, r8, r9, sl, fp, pc}
+.L31:
+	.align	2
+.L30:
+	.word	k_lut
+	.size	bmw_small_f1, .-bmw_small_f1
+	.align	2
+	.global	bmw224_init
+	.thumb
+	.thumb_func
+	.type	bmw224_init, %function
+bmw224_init:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	ldr	r3, .L36
+	mov	r2, r0
+	str	r3, [r0, #0]
+	add	r1, r0, #60
+.L33:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67372036
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L33
+	movs	r3, #0
+	str	r3, [r0, #64]
+	bx	lr
+.L37:
+	.align	2
+.L36:
+	.word	66051
+	.size	bmw224_init, .-bmw224_init
+	.align	2
+	.global	bmw256_init
+	.thumb
+	.thumb_func
+	.type	bmw256_init, %function
+bmw256_init:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	ldr	r3, .L42
+	mov	r2, r0
+	str	r3, [r0, #0]
+	add	r1, r0, #60
+.L39:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67372036
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L39
+	movs	r3, #0
+	str	r3, [r0, #64]
+	bx	lr
+.L43:
+	.align	2
+.L42:
+	.word	1078018627
+	.size	bmw256_init, .-bmw256_init
+	.align	2
+	.global	bmw256_ctx2hash
+	.thumb
+	.thumb_func
+	.type	bmw256_ctx2hash, %function
+bmw256_ctx2hash:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{lr}
+	adds	r1, r1, #32
+	movs	r2, #32
+	bl	memcpy
+	pop	{pc}
+	.size	bmw256_ctx2hash, .-bmw256_ctx2hash
+	.align	2
+	.global	bmw224_ctx2hash
+	.thumb
+	.thumb_func
+	.type	bmw224_ctx2hash, %function
+bmw224_ctx2hash:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{lr}
+	adds	r1, r1, #36
+	movs	r2, #28
+	bl	memcpy
+	pop	{pc}
+	.size	bmw224_ctx2hash, .-bmw224_ctx2hash
+	.align	2
+	.thumb
+	.thumb_func
+	.type	bmw_small_f2, %function
+bmw_small_f2:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{r4, r5, r6, r7, r8, lr}
+	mov	r8, #0
+	mov	r5, r0
+	mov	r6, r1
+	mov	r0, r8
+	mov	r1, r2
+.L49:
+	add	r3, r6, r0
+	ldr	r2, [r3, #64]
+	adds	r0, r0, #4
+	cmp	r0, #32
+	eor	r8, r8, r2
+	bne	.L49
+	mov	r7, r8
+	subs	r0, r0, #32
+.L50:
+	add	r3, r6, r0
+	ldr	r2, [r3, #96]
+	adds	r0, r0, #4
+	eors	r7, r7, r2
+	cmp	r0, #32
+	bne	.L50
+	movs	r2, #64
+	mov	r0, r5
+	bl	memcpy
+	ldr	r2, [r6, #64]
+	ldr	r3, [r5, #0]
+	movs	r0, #0
+	eor	r3, r3, r2, lsr #5
+	eor	r3, r3, r7, lsl #5
+	str	r3, [r5, #0]
+	ldr	r2, [r6, #68]
+	ldr	r3, [r5, #4]
+	eor	r3, r3, r2, lsl #8
+	eor	r3, r3, r7, lsr #7
+	str	r3, [r5, #4]
+	ldr	r2, [r6, #72]
+	ldr	r3, [r5, #8]
+	eor	r3, r3, r2, lsl #5
+	eor	r3, r3, r7, lsr #5
+	str	r3, [r5, #8]
+	ldr	r2, [r6, #76]
+	ldr	r3, [r5, #12]
+	eor	r3, r3, r2, lsl #5
+	eor	r3, r3, r7, lsr #1
+	str	r3, [r5, #12]
+	ldr	r2, [r6, #80]
+	ldr	r3, [r5, #16]
+	eors	r2, r2, r3
+	eor	r2, r2, r7, lsr #3
+	str	r2, [r5, #16]
+	ldr	r1, [r6, #84]
+	ldr	r3, [r5, #20]
+	eor	r3, r3, r1, lsr #6
+	eor	r3, r3, r7, lsl #6
+	str	r3, [r5, #20]
+	ldr	r2, [r6, #88]
+	ldr	r3, [r5, #24]
+	eor	r3, r3, r2, lsl #6
+	eor	r3, r3, r7, lsr #4
+	str	r3, [r5, #24]
+	ldr	r2, [r6, #92]
+	ldr	r3, [r5, #28]
+	eor	r3, r3, r2, lsl #2
+	eor	r3, r3, r7, lsr #11
+	str	r3, [r5, #28]
+.L51:
+	add	r1, r6, r0
+	ldr	r2, [r6, r0]
+	ldr	r3, [r1, #96]
+	eors	r2, r2, r3
+	ldr	r3, [r5, r0]
+	eor	r2, r2, r8
+	adds	r3, r3, r2
+	str	r3, [r5, r0]
+	adds	r0, r0, #4
+	cmp	r0, #32
+	bne	.L51
+	mov	lr, r5
+	mov	r4, r6
+	mov	ip, #4
+.L52:
+	ldr	r3, [lr, #32]
+	ldr	r0, [r4, #96]
+	and	r2, ip, #7
+	eors	r0, r0, r3
+	eors	r0, r0, r7
+	str	r0, [lr, #32]
+	ldr	r1, [r5, r2, lsl #2]
+	rsb	r3, ip, #27
+	add	r2, ip, #5
+	lsrs	r3, r1, r3
+	lsls	r1, r1, r2
+	add	ip, ip, #1
+	orrs	r3, r3, r1
+	adds	r3, r3, r0
+	adds	r4, r4, #4
+	cmp	ip, #12
+	str	r3, [lr, #32]
+	add	lr, lr, #4
+	bne	.L52
+	movs	r2, #28
+	add	r0, r6, #36
+	add	r1, r6, #64
+	bl	memxor
+	ldr	r3, [r6, #32]
+	ldr	r2, [r6, #92]
+	eors	r2, r2, r3
+	str	r2, [r6, #32]
+	ldr	r3, [r5, #32]
+	eor	r2, r2, r8, lsl #8
+	adds	r3, r3, r2
+	str	r3, [r5, #32]
+	ldr	r2, [r6, #36]
+	ldr	r3, [r5, #36]
+	eor	r2, r2, r8, lsr #6
+	adds	r3, r3, r2
+	str	r3, [r5, #36]
+	ldr	r2, [r6, #40]
+	ldr	r3, [r5, #40]
+	eor	r2, r2, r8, lsl #6
+	adds	r3, r3, r2
+	str	r3, [r5, #40]
+	ldr	r2, [r6, #44]
+	ldr	r3, [r5, #44]
+	eor	r2, r2, r8, lsl #4
+	adds	r3, r3, r2
+	str	r3, [r5, #44]
+	ldr	r2, [r6, #48]
+	ldr	r3, [r5, #48]
+	eor	r2, r2, r8, lsr #3
+	adds	r3, r3, r2
+	str	r3, [r5, #48]
+	ldr	r2, [r6, #52]
+	ldr	r3, [r5, #52]
+	eor	r2, r2, r8, lsr #4
+	adds	r3, r3, r2
+	str	r3, [r5, #52]
+	ldr	r2, [r6, #56]
+	ldr	r3, [r5, #56]
+	eor	r2, r2, r8, lsr #7
+	adds	r3, r3, r2
+	str	r3, [r5, #56]
+	ldr	r2, [r6, #60]
+	ldr	r3, [r5, #60]
+	eor	r2, r2, r8, lsr #2
+	adds	r3, r3, r2
+	str	r3, [r5, #60]
+	pop	{r4, r5, r6, r7, r8, pc}
+	.size	bmw_small_f2, .-bmw_small_f2
+	.align	2
+	.global	bmw_small_nextBlock
+	.thumb
+	.thumb_func
+	.type	bmw_small_nextBlock, %function
+bmw_small_nextBlock:
+	@ args = 0, pretend = 0, frame = 128
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{r4, r5, r6, lr}
+	mov	r5, r0
+	sub	sp, sp, #128
+	mov	r6, r1
+	mov	r0, sp
+	mov	r1, r5
+	mov	r2, r6
+	bl	bmw_small_f0
+	mov	r0, sp
+	mov	r1, r6
+	mov	r2, r5
+	bl	bmw_small_f1
+	mov	r0, r5
+	mov	r1, sp
+	mov	r2, r6
+	bl	bmw_small_f2
+	ldr	r3, [r5, #64]
+	mov	r4, sp
+	adds	r3, r3, #1
+	str	r3, [r5, #64]
+	add	sp, sp, #128
+	pop	{r4, r5, r6, pc}
+	.size	bmw_small_nextBlock, .-bmw_small_nextBlock
+	.align	2
+	.global	bmw256_nextBlock
+	.thumb
+	.thumb_func
+	.type	bmw256_nextBlock, %function
+bmw256_nextBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{lr}
+	bl	bmw_small_nextBlock
+	pop	{pc}
+	.size	bmw256_nextBlock, .-bmw256_nextBlock
+	.align	2
+	.global	bmw224_nextBlock
+	.thumb
+	.thumb_func
+	.type	bmw224_nextBlock, %function
+bmw224_nextBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{lr}
+	bl	bmw_small_nextBlock
+	pop	{pc}
+	.size	bmw224_nextBlock, .-bmw224_nextBlock
+	.align	2
+	.global	bmw_small_lastBlock
+	.thumb
+	.thumb_func
+	.type	bmw_small_lastBlock, %function
+bmw_small_lastBlock:
+	@ args = 0, pretend = 0, frame = 192
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{r4, r5, r6, r7, r8, sl, lr}
+	movw	r3, #511
+	uxth	r8, r2
+	cmp	r8, r3
+	sub	sp, sp, #192
+	mov	r6, r0
+	mov	sl, r1
+	bls	.L65
+	mov	r5, r1
+	mov	r4, r8
+	mov	r7, r3
+.L66:
+	mov	r1, r5
+	mov	r0, r6
+	bl	bmw_small_nextBlock
+	sub	r3, r4, #512
+	uxth	r4, r3
+	adds	r5, r5, #64
+	cmp	r4, r7
+	bhi	.L66
+	sub	r2, r8, #512
+	uxth	r2, r2
+	lsrs	r3, r2, #9
+	adds	r3, r3, #1
+	lsls	r3, r3, #6
+	lsl	r8, r2, #23
+	add	sl, sl, r3
+	lsr	r8, r8, #23
+.L65:
+	add	r5, sp, #128
+	movs	r1, #0
+	movs	r2, #64
+	mov	r0, r5
+	bl	memset
+	add	r2, r8, #7
+	asrs	r2, r2, #3
+	mov	r1, sl
+	mov	r0, r5
+	bl	memcpy
+	add	r3, sp, #192
+	add	ip, r3, r8, lsr #3
+	and	r1, r8, #7
+	movs	r3, #128
+	asrs	r3, r3, r1
+	ldrb	r2, [ip, #-64]	@ zero_extendqisi2
+	orrs	r3, r3, r2
+	strb	r3, [ip, #-64]
+	cmp	r8, #448
+	it	lt
+	ldrlt	r1, [r6, #64]
+	bge	.L74
+.L67:
+	mov	r2, #512
+	mov	r3, r8
+	mov	r4, #0
+	umlal	r3, r4, r2, r1
+	mov	r0, r6
+	str	r3, [r5, #56]
+	str	r4, [r5, #60]
+	mov	r1, r5
+	bl	bmw_small_nextBlock
+	movs	r2, #64
+	mov	r0, r5
+	movs	r1, #170
+	bl	memset
+	movs	r2, #0
+	movs	r3, #160
+.L68:
+	strb	r3, [r5, r2]
+	adds	r2, r2, #4
+	adds	r3, r3, #1
+	cmp	r2, #64
+	uxtb	r3, r3
+	bne	.L68
+	mov	r1, r5
+	mov	r0, sp
+	mov	r2, r6
+	bl	bmw_small_f0
+	mov	r2, r5
+	mov	r0, sp
+	mov	r1, r6
+	bl	bmw_small_f1
+	mov	r4, r6
+	mov	r0, r5
+	mov	r1, sp
+	mov	r2, r6
+	bl	bmw_small_f2
+	ldmia	r5!, {r0, r1, r2, r3}
+	stmia	r4!, {r0, r1, r2, r3}
+	mov	ip, r5
+	ldmia	ip!, {r0, r1, r2, r3}
+	stmia	r4!, {r0, r1, r2, r3}
+	ldmia	ip!, {r0, r1, r2, r3}
+	stmia	r4!, {r0, r1, r2, r3}
+	ldmia	ip, {r0, r1, r2, r3}
+	stmia	r4, {r0, r1, r2, r3}
+	add	sp, sp, #192
+	pop	{r4, r5, r6, r7, r8, sl, pc}
+.L74:
+	mov	r1, r5
+	mov	r0, r6
+	bl	bmw_small_nextBlock
+	ldr	r1, [r6, #64]
+	movs	r3, #0
+	subs	r1, r1, #1
+	str	r3, [sp, #128]
+	str	r3, [sp, #132]
+	str	r3, [sp, #136]
+	str	r3, [sp, #140]
+	str	r3, [sp, #144]
+	str	r3, [sp, #148]
+	str	r3, [sp, #152]
+	str	r3, [sp, #156]
+	str	r3, [sp, #160]
+	str	r3, [sp, #164]
+	str	r3, [sp, #168]
+	str	r3, [sp, #172]
+	str	r3, [sp, #176]
+	str	r3, [sp, #180]
+	str	r1, [r6, #64]
+	b	.L67
+	.size	bmw_small_lastBlock, .-bmw_small_lastBlock
+	.align	2
+	.global	bmw256
+	.thumb
+	.thumb_func
+	.type	bmw256, %function
+bmw256:
+	@ args = 0, pretend = 0, frame = 68
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{r4, r5, r6, r7, r8, r9, sl, lr}
+	ldr	r3, .L82
+	sub	sp, sp, #68
+	add	r6, sp, #68
+	mov	sl, r1
+	mov	r7, r2
+	mov	r9, r0
+	str	r3, [r6, #-68]!
+	mov	r2, sp
+	add	r1, sp, #60
+.L76:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67372036
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L76
+	movs	r3, #0
+	str	r3, [sp, #64]
+	movw	r3, #511
+	cmp	r7, r3
+	bls	.L77
+	mov	r5, sl
+	mov	r4, r7
+	mov	r8, r3
+.L78:
+	mov	r1, r5
+	mov	r0, sp
+	sub	r4, r4, #512
+	bl	bmw_small_nextBlock
+	adds	r5, r5, #64
+	cmp	r4, r8
+	bhi	.L78
+	sub	r2, r7, #512
+	lsrs	r3, r2, #9
+	adds	r3, r3, #1
+	lsls	r3, r3, #6
+	lsls	r7, r2, #23
+	add	sl, sl, r3
+	lsrs	r7, r7, #23
+.L77:
+	uxth	r2, r7
+	mov	r0, sp
+	mov	r1, sl
+	bl	bmw_small_lastBlock
+	mov	r0, r9
+	add	r1, sp, #32
+	movs	r2, #32
+	bl	memcpy
+	add	sp, sp, #68
+	pop	{r4, r5, r6, r7, r8, r9, sl, pc}
+.L83:
+	.align	2
+.L82:
+	.word	1078018627
+	.size	bmw256, .-bmw256
+	.align	2
+	.global	bmw224
+	.thumb
+	.thumb_func
+	.type	bmw224, %function
+bmw224:
+	@ args = 0, pretend = 0, frame = 68
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{r4, r5, r6, r7, r8, r9, sl, lr}
+	ldr	r3, .L91
+	sub	sp, sp, #68
+	add	r6, sp, #68
+	mov	sl, r1
+	mov	r7, r2
+	mov	r9, r0
+	str	r3, [r6, #-68]!
+	mov	r2, sp
+	add	r1, sp, #60
+.L85:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67372036
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L85
+	movs	r3, #0
+	str	r3, [sp, #64]
+	movw	r3, #511
+	cmp	r7, r3
+	bls	.L86
+	mov	r5, sl
+	mov	r4, r7
+	mov	r8, r3
+.L87:
+	mov	r1, r5
+	mov	r0, sp
+	sub	r4, r4, #512
+	bl	bmw_small_nextBlock
+	adds	r5, r5, #64
+	cmp	r4, r8
+	bhi	.L87
+	sub	r2, r7, #512
+	lsrs	r3, r2, #9
+	adds	r3, r3, #1
+	lsls	r3, r3, #6
+	lsls	r7, r2, #23
+	add	sl, sl, r3
+	lsrs	r7, r7, #23
+.L86:
+	uxth	r2, r7
+	mov	r0, sp
+	mov	r1, sl
+	bl	bmw_small_lastBlock
+	mov	r0, r9
+	add	r1, sp, #36
+	movs	r2, #28
+	bl	memcpy
+	add	sp, sp, #68
+	pop	{r4, r5, r6, r7, r8, r9, sl, pc}
+.L92:
+	.align	2
+.L91:
+	.word	66051
+	.size	bmw224, .-bmw224
+	.align	2
+	.global	bmw256_lastBlock
+	.thumb
+	.thumb_func
+	.type	bmw256_lastBlock, %function
+bmw256_lastBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{lr}
+	uxth	r2, r2
+	bl	bmw_small_lastBlock
+	pop	{pc}
+	.size	bmw256_lastBlock, .-bmw256_lastBlock
+	.align	2
+	.global	bmw224_lastBlock
+	.thumb
+	.thumb_func
+	.type	bmw224_lastBlock, %function
+bmw224_lastBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	push	{lr}
+	uxth	r2, r2
+	bl	bmw_small_lastBlock
+	pop	{pc}
+	.size	bmw224_lastBlock, .-bmw224_lastBlock
+	.section	.rodata
+	.align	2
+	.type	k_lut, %object
+	.size	k_lut, 64
+k_lut:
+	.word	1431655760
+	.word	1521134245
+	.word	1610612730
+	.word	1700091215
+	.word	1789569700
+	.word	1879048185
+	.word	1968526670
+	.word	2058005155
+	.word	2147483640
+	.word	-2058005171
+	.word	-1968526686
+	.word	-1879048201
+	.word	-1789569716
+	.word	-1700091231
+	.word	-1610612746
+	.word	-1521134261
+	.ident	"GCC: (GNU) 4.3.2"
diff --git a/bmw/bmw_small-asm.S b/bmw/bmw_small-asm.S
new file mode 100644
index 0000000..b04635e
--- /dev/null
+++ b/bmw/bmw_small-asm.S
@@ -0,0 +1,220 @@
+/* bmw_small-asm.S */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+ * \file    bmw_small-asm.S
+ * \author  Daniel Otte
+ * \email   daniel.otte@rub.de
+ * \date    2010-05-23
+ * \license GPLv3 or later
+ *
+ */
+.syntax unified
+.text
+.thumb
+.align 2
+.thumb_func
+ /*
+#define S32_1(x) ( (SHR32((x),   1)) ^ \
+	               (SHL32((x),   2)) ^ \
+	               (ROTL32((x),  8)) ^ \
+	               (ROTR32((x),  9)) )
+
+#define S32_2(x) ( (SHR32((x),   2)) ^ \
+	               (SHL32((x),   1)) ^ \
+	               (ROTL32((x), 12)) ^ \
+	               (ROTR32((x),  7)) )
+
+#define S32_3(x) ( (SHR32((x),   2)) ^ \
+	               (SHL32((x),   2)) ^ \
+	               (ROTL32((x), 15)) ^ \
+	               (ROTR32((x),  3)) )
+
+#define S32_4(x) ( (SHR32((x),   1)) ^ (x))
+
+#define S32_5(x) ( (SHR32((x),   2)) ^ (x))
+
+*/
+
+.global bmw_s32_0
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_s32_0, %function
+bmw_s32_0:
+ 	mov r1, r0
+ 	lsrs r0, r0, #1
+ 	eor r0, r0, r1, lsl #3
+ 	eor r0, r0, r1, ror #28
+ 	eor r0, r0, r1, ror #13
+	bx lr
+
+.global bmw_s32_1
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_s32_1, %function
+bmw_s32_1:
+ 	mov r1, r0
+ 	lsrs r0, r0, #1
+ 	eor r0, r0, r1, lsl #2
+ 	eor r0, r0, r1, ror #24
+ 	eor r0, r0, r1, ror #9
+	bx lr
+
+.global bmw_s32_2
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_s32_2, %function
+bmw_s32_2:
+ 	mov r1, r0
+ 	lsrs r0, r0, #2
+ 	eor r0, r0, r1, lsl #1
+ 	eor r0, r0, r1, ror #20
+ 	eor r0, r0, r1, ror #7
+	bx lr
+
+.global bmw_s32_3
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_s32_3, %function
+bmw_s32_3:
+ 	mov r1, r0
+ 	lsrs r0, r0, #2
+ 	eor r0, r0, r1, lsl #2
+ 	eor r0, r0, r1, ror #17
+ 	eor r0, r0, r1, ror #3
+	bx lr
+
+.global bmw_s32_4
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_s32_4, %function
+bmw_s32_4:
+	eor r0, r0, r0, lsr #1
+	bx lr
+
+.global bmw_s32_5
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_s32_5, %function
+bmw_s32_5:
+	eor r0, r0, r0, lsr #2
+	bx lr
+
+
+
+.global bmw_small_f0
+.text
+.thumb
+.align 2
+.thumb_func
+.type bmw_small_f0, %function
+/*
+ * param q:  r0
+ * param h:  r1
+ * param m:  r2
+ */
+bmw_small_f0:
+	push {r4-r11, r14}
+	sub sp, sp, #64
+	mov r3, sp
+	adds r3, r3, #4
+10:
+	ldmia r1!, {r4,r6,r8,r10}
+	ldmia r2!, {r5,r7,r9,r11}
+	eors r4, r5
+	eors r6, r7
+	eors r8, r9
+	eors r10, r11
+	stmia r3!, {r4,r6,r8,r10}
+
+	ldmia r1!, {r4,r6,r8,r10}
+	ldmia r2!, {r5,r7,r9,r11}
+	eors r4, r5
+	eors r6, r7
+	eors r8, r9
+	eors r10, r11
+	stmia r3!, {r4,r6,r8,r10}
+
+	ldmia r1!, {r4,r6,r8,r10}
+	ldmia r2!, {r5,r7,r9,r11}
+	eors r4, r5
+	eors r6, r7
+	eors r8, r9
+	eors r10, r11
+	stmia r3!, {r4,r6,r8,r10}
+
+	ldmia r1!, {r4,r6,r8,r10}
+	ldmia r2!, {r5,r7,r9,r11}
+	eors r4, r5
+	eors r6, r7
+	eors r8, r9
+	eors r10, r11
+	stmia r3!, {r4,r6,r8,r10}
+/* --- */
+	subs r1, r1, #64
+	subs r3, r3, #64
+/*
+	q[ 0] = (+ h[ 5] - h[ 7] + h[10] + h[13] + h[14]);
+	q[ 3] = (+ h[ 8] - h[10] + h[13] + h[ 0] - h[ 1]);
+	q[ 6] = (- h[11] + h[13] - h[ 0] - h[ 3] + h[ 4]);
+	q[ 9] = (+ h[14] + h[ 0] - h[ 3] + h[ 6] - h[ 7]);
+	q[12] = (+ h[ 1] + h[ 3] - h[ 6] - h[ 9] + h[10]);
+	q[15] = (- h[ 4] - h[ 6] - h[ 9] + h[12] + h[13]);
+	q[ 2] = (+ h[ 7] + h[ 9] - h[12] + h[15] + h[ 0]);
+	q[ 5] = (+ h[10] - h[12] + h[15] - h[ 2] + h[ 3]);
+	q[ 8] = (+ h[13] - h[15] + h[ 2] - h[ 5] - h[ 6]);
+	q[11] = (- h[ 0] - h[ 2] - h[ 5] + h[ 8] + h[ 9]);
+	q[14] = (+ h[ 3] - h[ 5] + h[ 8] - h[11] - h[12]);
+	q[ 1] = (+ h[ 6] - h[ 8] + h[11] + h[14] - h[15]);
+	q[ 4] = (+ h[ 9] - h[11] - h[14] + h[ 1] + h[ 2]);
+	q[ 7] = (- h[12] - h[14] + h[ 1] - h[ 4] - h[ 5]);
+	q[10] = (+ h[15] - h[ 1] - h[ 4] - h[ 7] + h[ 8]);
+	q[13] = (+ h[ 2] + h[ 4] + h[ 7] + h[10] + h[11]);
+*/
+	ldr r4,  [r3,  #(5*4)]
+	ldr r5,  [r3,  #(7*4)]
+	ldr r6,  [r3, #(10*4)]
+	ldr r7,  [r3, #(13*4)]
+	ldr r8,  [r3, #(14*4)]
+	ldr r9,  [r3, #(8*4)]
+	ldr r10, [r3, #(11*4)]
+	subs r2, r4, r5
+	adds r2, r2, r6
+	adds r2, r2, r7
+	adds r2, r2, r8
+	str r2, [r0, #0]
+	ldr r4, [r3, #0]
+	ldr r5, [r3, #1]
+	subs r2, r9, r6
+	adds r2, r2, r7
+	adds r2, r2, r4
+	subs r2, r2, r5
+	add sp, sp, #64
+	pop {r4-r11, pc}
diff --git a/bmw/bmw_small_speed.s b/bmw/bmw_small_speed.s
new file mode 100644
index 0000000..a4e2874
--- /dev/null
+++ b/bmw/bmw_small_speed.s
@@ -0,0 +1,1994 @@
+	.file	"bmw_small_speed.c"
+	.text
+	.align	2
+	.type	bmw_small_f1, %function
+bmw_small_f1:
+	@ args = 0, pretend = 0, frame = 24
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp}
+	ldmib	r0, {r5, r6}	@ phole ldm
+	ldr	r7, [r0, #0]
+	ldr	r8, [r0, #12]
+	mov	r9, r5, lsr #2
+	mov	r3, r6, lsr #2
+	ldr	sl, [r0, #16]
+	eor	r9, r9, r5, asl #1
+	eor	r3, r3, r6, asl #2
+	mov	ip, r7, lsr #1
+	ldr	fp, [r0, #20]
+	eor	r9, r9, r5, ror #20
+	eor	r3, r3, r6, ror #17
+	eor	ip, ip, r7, asl #2
+	mov	r4, r8, lsr #1
+	eor	r3, r3, r6, ror #3
+	eor	r9, r9, r5, ror #7
+	ldr	r6, [r0, #24]
+	eor	ip, ip, r7, ror #24
+	eor	r4, r4, r8, asl #3
+	mov	r5, sl, lsr #1
+	eor	ip, ip, r7, ror #9
+	add	r9, r9, r3
+	ldr	r7, [r0, #28]
+	eor	r4, r4, r8, ror #28
+	eor	r5, r5, sl, asl #2
+	mov	r3, fp, lsr #2
+	eor	r4, r4, r8, ror #13
+	add	r9, r9, ip
+	eor	r5, r5, sl, ror #24
+	eor	r3, r3, fp, asl #1
+	mov	ip, r6, lsr #2
+	eor	r5, r5, sl, ror #9
+	add	r9, r9, r4
+	eor	r3, r3, fp, ror #20
+	eor	ip, ip, r6, asl #2
+	mov	r4, r7, lsr #1
+	ldr	r8, [r0, #32]
+	eor	r3, r3, fp, ror #7
+	add	r9, r9, r5
+	eor	ip, ip, r6, ror #17
+	eor	r4, r4, r7, asl #3
+	ldr	sl, [r0, #36]
+	eor	ip, ip, r6, ror #3
+	add	r9, r9, r3
+	ldr	r6, [r0, #44]
+	eor	r4, r4, r7, ror #28
+	ldr	fp, [r0, #40]
+	eor	r4, r4, r7, ror #13
+	mov	r5, r8, lsr #1
+	ldr	r7, [r0, #48]
+	add	r9, r9, ip
+	eor	r5, r5, r8, asl #2
+	mov	r3, sl, lsr #2
+	add	r9, r9, r4
+	mov	r4, r6, lsr #1
+	eor	r5, r5, r8, ror #24
+	eor	r3, r3, sl, asl #1
+	mov	ip, fp, lsr #2
+	eor	r4, r4, r6, asl #3
+	mov	r6, r7, lsr #1
+	eor	r5, r5, r8, ror #9
+	eor	r3, r3, sl, ror #20
+	ldr	r8, [r0, #44]
+	eor	ip, ip, fp, asl #2
+	eor	r6, r6, r7, asl #2
+	eor	r3, r3, sl, ror #7
+	add	r9, r9, r5
+	eor	ip, ip, fp, ror #17
+	eor	r6, r6, r7, ror #24
+	ldr	sl, [r0, #52]
+	eor	ip, ip, fp, ror #3
+	eor	r6, r6, r7, ror #9
+	add	r9, r9, r3
+	ldr	r7, [r0, #8]
+	eor	r4, r4, r8, ror #28
+	eor	r4, r4, r8, ror #13
+	add	r9, r9, ip
+	mov	r3, sl, lsr #2
+	add	r9, r9, r4
+	mov	r5, r7, lsr #2
+	ldr	r4, [r0, #60]
+	ldr	r7, [r0, #4]
+	eor	r3, r3, sl, asl #1
+	add	r9, r9, r6
+	ldr	r6, [r0, #52]
+	ldr	ip, [r1, #0]
+	ldr	fp, [r0, #56]
+	eor	r3, r3, sl, ror #20
+	mov	sl, r4, lsr #1
+	mov	r4, r7, lsr #1
+	ldr	r7, .L3
+	sub	sp, sp, #24
+	eor	r3, r3, r6, ror #7
+	str	r3, [sp, #0]
+	mov	r8, fp, lsr #2
+	ldr	r3, [r0, #60]
+	add	r7, r7, ip, ror #31
+	ldr	ip, [r0, #56]
+	eor	r8, r8, fp, asl #2
+	ldr	r6, [r0, #8]
+	eor	r8, r8, ip, ror #17
+	eor	sl, sl, r3, asl #3
+	ldr	ip, [r0, #4]
+	ldr	r3, [r0, #12]
+	eor	r5, r5, r6, asl #1
+	eor	r6, r4, ip, asl #2
+	mov	ip, r3, lsr #2
+	ldr	r3, [sp, #0]
+	add	r9, r9, r3
+	ldr	r3, [r0, #56]
+	ldr	fp, [r1, #12]
+	eor	r8, r8, r3, ror #3
+	ldr	r3, [r0, #8]
+	add	r7, r7, fp, ror #28
+	eor	r5, r5, r3, ror #20
+	ldr	fp, [r0, #60]
+	ldr	r3, [r0, #4]
+	ldr	r4, [r1, #40]
+	eor	sl, sl, fp, ror #28
+	eor	fp, r6, r3, ror #24
+	ldr	r6, [r0, #12]
+	ldr	r3, [r0, #16]
+	eor	ip, ip, r6, asl #2
+	add	r9, r9, r8
+	mov	r6, r3, lsr #1
+	ldr	r8, [r0, #60]
+	ldr	r3, [r0, #8]
+	sub	r7, r7, r4, ror #21
+	ldr	r4, [r0, #4]
+	eor	sl, sl, r8, ror #13
+	eor	r5, r5, r3, ror #7
+	eor	r8, fp, r4, ror #9
+	ldr	r3, [r0, #16]
+	ldr	fp, [r0, #12]
+	add	r9, r9, sl
+	ldr	sl, [r0, #16]
+	eor	ip, ip, fp, ror #17
+	eor	r6, r6, r3, asl #3
+	ldr	fp, [r0, #20]
+	add	r5, r5, r8
+	ldr	r8, [r0, #12]
+	ldr	r3, [r2, #28]
+	eor	r6, r6, sl, ror #28
+	eor	ip, ip, r8, ror #3
+	eor	r6, r6, sl, ror #13
+	ldr	r8, [r0, #24]
+	ldr	sl, [r0, #20]
+	mov	r4, fp, lsr #1
+	eor	r7, r7, r3
+	eor	r4, r4, fp, asl #2
+	add	r9, r9, r7
+	mov	r3, r8, lsr #2
+	eor	r4, r4, sl, ror #24
+	ldr	fp, [r0, #32]
+	ldr	r7, [r0, #36]
+	eor	r4, r4, sl, ror #9
+	eor	r3, r3, r8, asl #1
+	ldr	r8, [r0, #28]
+	str	r9, [r0, #64]
+	ldr	sl, [r0, #24]
+	add	r5, r5, ip
+	add	r5, r5, r6
+	eor	r3, r3, sl, ror #20
+	eor	r3, r3, sl, ror #7
+	mov	ip, r8, lsr #2
+	add	r5, r5, r4
+	eor	ip, ip, r8, asl #2
+	mov	r6, fp, lsr #1
+	add	r5, r5, r3
+	ldr	r3, [r0, #28]
+	eor	ip, ip, r8, ror #17
+	eor	r6, r6, fp, asl #3
+	eor	ip, ip, r3, ror #3
+	mov	r8, r7, lsr #1
+	ldr	r3, [r0, #40]
+	eor	r6, r6, fp, ror #28
+	eor	r6, r6, fp, ror #13
+	eor	r8, r8, r7, asl #2
+	add	r5, r5, ip
+	mov	sl, r3, lsr #2
+	eor	r8, r8, r7, ror #24
+	add	r5, r5, r6
+	ldr	r6, [r0, #40]
+	ldr	r4, [r1, #16]
+	eor	r8, r8, r7, ror #9
+	eor	sl, sl, r3, asl #1
+	ldr	fp, [r0, #44]
+	ldr	r3, [r1, #4]
+	eor	sl, sl, r6, ror #20
+	add	r5, r5, r8
+	ldr	r6, [r0, #48]
+	ldr	r8, [r0, #40]
+	mov	r4, r4, ror #27
+	eor	sl, sl, r8, ror #7
+	mov	ip, fp, lsr #2
+	mov	r7, r6, lsr #1
+	add	r4, r4, r3, ror #30
+	ldr	r3, [r0, #44]
+	eor	ip, ip, fp, asl #2
+	eor	r7, r7, r6, asl #3
+	add	r5, r5, sl
+	ldr	r6, [r0, #52]
+	ldr	sl, [r0, #44]
+	eor	ip, ip, r3, ror #17
+	ldr	fp, [r0, #56]
+	eor	ip, ip, sl, ror #3
+	mov	r3, r6, lsr #1
+	add	r6, r0, #48
+	ldmia	r6, {r6, sl}	@ phole ldm
+	ldr	r8, [r0, #60]
+	add	r5, r5, ip
+	ldr	ip, [r0, #48]
+	eor	r7, r7, r6, ror #28
+	eor	r3, r3, sl, asl #2
+	mov	r6, fp, lsr #2
+	add	r4, r4, #1509949440
+	eor	r7, r7, ip, ror #13
+	eor	r3, r3, sl, ror #24
+	eor	r6, r6, fp, asl #1
+	mov	ip, r8, lsr #2
+	add	r4, r4, #11141120
+	eor	r3, r3, sl, ror #9
+	add	r5, r5, r7
+	ldr	sl, [r1, #44]
+	eor	r6, r6, fp, ror #20
+	eor	ip, ip, r8, asl #2
+	add	r4, r4, #43520
+	ldr	r7, [r2, #32]
+	eor	r6, r6, fp, ror #7
+	add	r5, r5, r3
+	eor	ip, ip, r8, ror #17
+	mov	r3, r9, lsr #1
+	add	r4, r4, #165
+	eor	ip, ip, r8, ror #3
+	add	r5, r5, r6
+	sub	r4, r4, sl, ror #20
+	eor	r3, r3, r9, asl #3
+	eor	r4, r4, r7
+	add	r5, r5, ip
+	eor	r3, r3, r9, ror #28
+	eor	r3, r3, r9, ror #13
+	add	r5, r5, r4
+	ldr	ip, [r0, #12]
+	add	r5, r5, r3
+	ldr	r3, [r0, #20]
+	str	r5, [r0, #68]
+	ldr	r4, [r0, #8]
+	ldr	r6, [r0, #28]
+	ldr	r8, [r0, #16]
+	mov	ip, ip, ror #29
+	ldr	r7, [r0, #24]
+	ldr	sl, [r0, #36]
+	add	ip, ip, r3, ror #25
+	add	r8, r8, r4
+	ldr	r3, [r1, #20]
+	ldr	r4, [r0, #32]
+	add	ip, ip, r6, ror #19
+	ldr	r6, [r0, #44]
+	ldr	fp, [r1, #8]
+	add	r8, r8, r7
+	add	ip, ip, sl, ror #16
+	ldr	r7, [r0, #40]
+	add	r9, r0, #48
+	ldmia	r9, {r9, sl}	@ phole ldm
+	add	r8, r8, r4
+	add	ip, ip, r6, ror #13
+	ldr	r4, [r0, #64]
+	ldr	r6, [r0, #60]
+	mov	r3, r3, ror #26
+	add	r8, r8, r7
+	add	ip, ip, sl, ror #9
+	ldr	r7, [r0, #56]
+	ldr	sl, [r1, #48]
+	add	r3, r3, fp, ror #29
+	add	r8, r8, r9
+	add	ip, ip, r6, ror #5
+	eor	r4, r4, r4, lsr #1
+	ldr	r6, [r2, #36]
+	sub	r3, r3, #-1610612730
+	add	r8, r8, r7
+	add	ip, ip, r4
+	sub	r3, r3, sl, ror #19
+	eor	r3, r3, r6
+	add	ip, ip, r8
+	add	ip, ip, r3
+	eor	r5, r5, r5, lsr #2
+	add	ip, ip, r5
+	str	ip, [r0, #72]
+	ldr	r5, [r0, #16]
+	ldr	r4, [r0, #24]
+	ldr	r3, [r1, #24]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #20]
+	mov	r5, r5, ror #29
+	ldr	r9, [r1, #12]
+	add	r5, r5, r4, ror #25
+	add	r4, r0, #28
+	ldmia	r4, {r4, sl}	@ phole ldm
+	add	r7, r7, r6
+	mov	r3, r3, ror #25
+	add	r6, r0, #36
+	ldmia	r6, {r6, fp}	@ phole ldm
+	add	r3, r3, r9, ror #28
+	add	r7, r7, r4
+	ldr	r9, [r0, #44]
+	add	r5, r5, sl, ror #19
+	add	r7, r7, r6
+	ldr	sl, [r0, #48]
+	add	r5, r5, fp, ror #16
+	add	r7, r7, r9
+	add	r3, r3, #1711276032
+	ldr	r9, [r0, #56]
+	ldr	fp, [r0, #52]
+	ldr	r6, [r0, #64]
+	add	r5, r5, sl, ror #13
+	ldr	r4, [r0, #68]
+	sub	r3, r3, #11141120
+	ldr	sl, [r0, #60]
+	add	r5, r5, r9, ror #9
+	sub	r3, r3, #43520
+	ldr	r9, [r1, #52]
+	add	r7, r7, fp
+	add	r5, r5, r6, ror #5
+	eor	r4, r4, r4, lsr #1
+	ldr	r6, [r2, #40]
+	sub	r3, r3, #177
+	add	r7, r7, sl
+	add	r5, r5, r4
+	sub	r3, r3, r9, ror #18
+	eor	r3, r3, r6
+	add	r5, r5, r7
+	add	r5, r5, r3
+	eor	ip, ip, ip, lsr #2
+	add	r5, r5, ip
+	str	r5, [r0, #76]
+	ldr	ip, [r0, #20]
+	ldr	r4, [r0, #28]
+	ldr	r3, [r1, #28]
+	ldr	r6, [r0, #36]
+	mov	ip, ip, ror #29
+	ldr	sl, [r1, #16]
+	add	ip, ip, r4, ror #25
+	ldr	r4, [r0, #44]
+	add	ip, ip, r6, ror #19
+	mov	r3, r3, ror #24
+	add	r3, r3, sl, ror #27
+	add	ip, ip, r4, ror #16
+	ldr	sl, [r0, #60]
+	ldr	r9, [r0, #68]
+	add	ip, ip, fp, ror #13
+	add	r3, r3, #1778384896
+	add	ip, ip, sl, ror #9
+	add	r3, r3, #11141120
+	ldr	r4, [r0, #72]
+	add	ip, ip, r9, ror #5
+	add	r3, r3, #43520
+	ldr	r9, [r1, #56]
+	ldr	fp, [r0, #64]
+	ldr	sl, [r2, #44]
+	ldr	r6, [r0, #8]
+	add	r3, r3, #164
+	sub	r3, r3, r9, ror #17
+	eor	r4, r4, r4, lsr #1
+	eor	r3, r3, sl
+	rsb	r6, r6, fp
+	add	ip, ip, r4
+	add	r6, r6, r8
+	add	ip, ip, r3
+	add	ip, ip, r6
+	eor	r5, r5, r5, lsr #2
+	str	r6, [sp, #4]
+	add	ip, ip, r5
+	ldr	r4, [r0, #24]
+	str	ip, [r0, #80]
+	ldr	r5, [r0, #32]
+	ldr	r6, [r0, #40]
+	mov	r4, r4, ror #29
+	ldr	r3, [r1, #32]
+	add	r4, r4, r5, ror #25
+	ldr	r5, [r0, #48]
+	ldr	r8, [r1, #20]
+	add	r4, r4, r6, ror #19
+	ldr	r6, [r0, #56]
+	add	r4, r4, r5, ror #16
+	mov	r3, r3, ror #23
+	ldr	r9, [r1, #60]
+	add	r4, r4, r6, ror #13
+	add	r3, r3, r8, ror #26
+	ldr	r5, [r0, #76]
+	ldr	r8, [r0, #72]
+	ldr	sl, [r2, #48]
+	add	r4, r4, fp, ror #9
+	ldr	r6, [r0, #12]
+	ldr	fp, [r0, #68]
+	sub	r3, r3, #-1879048185
+	add	r4, r4, r8, ror #5
+	sub	r3, r3, r9, ror #16
+	eor	r5, r5, r5, lsr #1
+	eor	r3, r3, sl
+	rsb	r6, r6, fp
+	add	r4, r4, r5
+	add	fp, r6, r7
+	add	r4, r4, r3
+	add	r4, r4, fp
+	eor	ip, ip, ip, lsr #2
+	add	r4, r4, ip
+	str	r4, [r0, #84]
+	ldr	r5, [r0, #28]
+	ldr	r3, [r1, #36]
+	ldr	r7, [r1, #24]
+	ldr	r6, [r0, #36]
+	ldr	ip, [r0, #44]
+	mov	r5, r5, ror #29
+	mov	r3, r3, ror #22
+	add	r5, r5, r6, ror #25
+	add	r3, r3, r7, ror #25
+	ldr	r6, [r0, #52]
+	add	r5, r5, ip, ror #19
+	add	r3, r3, #1979711488
+	ldr	ip, [r0, #60]
+	add	r5, r5, r6, ror #16
+	sub	r3, r3, #11141120
+	ldr	r6, [r0, #68]
+	ldr	sl, [r1, #0]
+	ldr	r8, [r0, #76]
+	add	r5, r5, ip, ror #13
+	sub	r3, r3, #43520
+	ldr	ip, [r0, #80]
+	ldr	r9, [r0, #72]
+	ldr	r7, [r2, #52]
+	add	r5, r5, r6, ror #9
+	sub	r3, r3, #178
+	ldr	r6, [r0, #16]
+	add	r5, r5, r8, ror #5
+	sub	r3, r3, sl, ror #31
+	eor	ip, ip, ip, lsr #1
+	ldr	sl, [sp, #4]
+	eor	r3, r3, r7
+	rsb	r6, r6, r9
+	add	r5, r5, ip
+	add	r6, r6, sl
+	add	r5, r5, r3
+	add	r5, r5, r6
+	eor	r4, r4, r4, lsr #2
+	add	r5, r5, r4
+	str	r5, [r0, #88]
+	ldr	ip, [r0, #32]
+	ldr	r3, [r1, #40]
+	ldr	r7, [r1, #28]
+	ldr	r4, [r0, #40]
+	str	r6, [sp, #8]
+	mov	ip, ip, ror #29
+	ldr	r6, [r0, #48]
+	mov	r3, r3, ror #21
+	add	ip, ip, r4, ror #25
+	add	r3, r3, r7, ror #24
+	ldr	r4, [r0, #56]
+	add	ip, ip, r6, ror #19
+	add	r3, r3, #2063597568
+	ldr	r6, [r0, #64]
+	add	ip, ip, r4, ror #16
+	sub	r3, r3, #5570560
+	ldr	sl, [r1, #4]
+	ldr	r8, [r0, #80]
+	add	ip, ip, r6, ror #13
+	ldr	r4, [r0, #84]
+	sub	r3, r3, #21760
+	ldr	r7, [r2, #56]
+	ldr	r6, [r0, #20]
+	add	ip, ip, r9, ror #9
+	sub	r3, r3, #93
+	ldr	r9, [r0, #76]
+	add	ip, ip, r8, ror #5
+	sub	r3, r3, sl, ror #30
+	eor	r4, r4, r4, lsr #1
+	eor	r3, r3, r7
+	rsb	r9, r6, r9
+	add	ip, ip, r4
+	add	r9, r9, fp
+	add	ip, ip, r3
+	add	ip, ip, r9
+	eor	r5, r5, r5, lsr #2
+	add	ip, ip, r5
+	ldr	r4, [r0, #36]
+	str	ip, [r0, #92]
+	ldr	r5, [r0, #44]
+	ldr	r6, [r0, #52]
+	mov	r4, r4, ror #29
+	ldr	r3, [r1, #44]
+	add	r4, r4, r5, ror #25
+	ldr	r5, [r0, #60]
+	ldr	r7, [r1, #32]
+	add	r4, r4, r6, ror #19
+	ldr	r6, [r0, #68]
+	ldr	r8, [r0, #76]
+	add	r4, r4, r5, ror #16
+	mov	r3, r3, ror #20
+	ldr	sl, [r1, #8]
+	ldr	fp, [r0, #80]
+	add	r4, r4, r6, ror #13
+	add	r3, r3, r7, ror #23
+	ldr	r5, [r0, #88]
+	ldr	r7, [r0, #84]
+	ldr	r6, [r0, #24]
+	add	r4, r4, r8, ror #9
+	sub	r3, r3, #-2147483640
+	ldr	r8, [r2, #60]
+	add	r4, r4, r7, ror #5
+	sub	r3, r3, sl, ror #29
+	eor	r5, r5, r5, lsr #1
+	rsb	r6, r6, fp
+	ldr	fp, [sp, #8]
+	eor	r3, r3, r8
+	add	r4, r4, r5
+	add	r6, r6, fp
+	add	r4, r4, r3
+	add	r4, r4, r6
+	eor	ip, ip, ip, lsr #2
+	add	r4, r4, ip
+	str	r4, [r0, #96]
+	ldr	r5, [r0, #40]
+	ldr	r3, [r1, #48]
+	ldr	r7, [r1, #36]
+	str	r6, [sp, #12]
+	ldr	r6, [r0, #48]
+	ldr	ip, [r0, #56]
+	mov	r5, r5, ror #29
+	mov	r3, r3, ror #19
+	add	r5, r5, r6, ror #25
+	add	r3, r3, r7, ror #22
+	ldr	r6, [r0, #64]
+	add	r5, r5, ip, ror #19
+	add	r3, r3, #-2063597568
+	ldr	ip, [r0, #72]
+	add	r5, r5, r6, ror #16
+	add	r3, r3, #5570560
+	ldr	r6, [r0, #80]
+	ldr	sl, [r1, #12]
+	ldr	r8, [r0, #88]
+	add	r5, r5, ip, ror #13
+	add	r3, r3, #21760
+	ldr	ip, [r0, #92]
+	ldr	fp, [r0, #84]
+	ldr	r7, [r2, #0]
+	add	r5, r5, r6, ror #9
+	add	r3, r3, #77
+	ldr	r6, [r0, #28]
+	add	r5, r5, r8, ror #5
+	sub	r3, r3, sl, ror #28
+	eor	ip, ip, ip, lsr #1
+	eor	r3, r3, r7
+	rsb	r6, r6, fp
+	add	r5, r5, ip
+	add	r6, r6, r9
+	add	r5, r5, r3
+	add	r5, r5, r6
+	eor	r4, r4, r4, lsr #2
+	add	r5, r5, r4
+	str	r5, [r0, #100]
+	ldr	ip, [r0, #44]
+	ldr	r3, [r1, #52]
+	ldr	r4, [r0, #52]
+	ldr	r7, [r1, #40]
+	str	r6, [sp, #16]
+	mov	ip, ip, ror #29
+	ldr	r6, [r0, #60]
+	add	ip, ip, r4, ror #25
+	mov	r3, r3, ror #18
+	ldr	r4, [r0, #68]
+	add	r3, r3, r7, ror #21
+	add	ip, ip, r6, ror #19
+	ldr	r6, [r0, #76]
+	add	ip, ip, r4, ror #16
+	add	r3, r3, #-1979711488
+	ldr	r8, [r0, #92]
+	add	ip, ip, r6, ror #13
+	ldr	r4, [r0, #96]
+	add	r3, r3, #11141120
+	ldr	sl, [r1, #16]
+	add	ip, ip, fp, ror #9
+	add	r3, r3, #43520
+	ldr	r7, [r2, #4]
+	ldr	r6, [r0, #32]
+	ldr	r9, [r0, #88]
+	add	ip, ip, r8, ror #5
+	eor	r4, r4, r4, lsr #1
+	add	r3, r3, #162
+	sub	r3, r3, sl, ror #27
+	add	ip, ip, r4
+	ldr	r4, [sp, #12]
+	eor	r3, r3, r7
+	rsb	r9, r6, r9
+	add	r9, r9, r4
+	add	ip, ip, r3
+	add	ip, ip, r9
+	eor	r5, r5, r5, lsr #2
+	add	ip, ip, r5
+	ldr	r4, [r0, #48]
+	str	ip, [r0, #104]
+	ldr	r5, [r0, #56]
+	ldr	r6, [r0, #64]
+	mov	r4, r4, ror #29
+	ldr	r3, [r1, #56]
+	add	r4, r4, r5, ror #25
+	ldr	r5, [r0, #72]
+	ldr	r7, [r1, #44]
+	add	r4, r4, r6, ror #19
+	ldr	r6, [r0, #80]
+	ldr	r8, [r0, #88]
+	add	r4, r4, r5, ror #16
+	mov	r3, r3, ror #17
+	add	r4, r4, r6, ror #13
+	add	r3, r3, r7, ror #20
+	ldr	r5, [r0, #100]
+	ldr	r7, [r0, #96]
+	ldr	sl, [r1, #20]
+	add	r4, r4, r8, ror #9
+	ldr	fp, [r0, #92]
+	ldr	r8, [r2, #8]
+	ldr	r6, [r0, #36]
+	add	r4, r4, r7, ror #5
+	eor	r5, r5, r5, lsr #1
+	sub	r3, r3, #1879048201
+	sub	r3, r3, sl, ror #26
+	add	r4, r4, r5
+	ldr	r5, [sp, #16]
+	eor	r3, r3, r8
+	rsb	r6, r6, fp
+	add	r6, r6, r5
+	add	r4, r4, r3
+	add	r4, r4, r6
+	eor	ip, ip, ip, lsr #2
+	add	r4, r4, ip
+	str	r4, [r0, #108]
+	ldr	r5, [r0, #52]
+	ldr	r3, [r1, #60]
+	ldr	r7, [r1, #48]
+	str	r6, [sp, #20]
+	ldr	r6, [r0, #60]
+	ldr	ip, [r0, #68]
+	mov	r5, r5, ror #29
+	mov	r3, r3, ror #16
+	add	r5, r5, r6, ror #25
+	add	r3, r3, r7, ror #19
+	ldr	r6, [r0, #76]
+	add	r5, r5, ip, ror #19
+	add	r3, r3, #-1795162112
+	ldr	ip, [r0, #84]
+	add	r5, r5, r6, ror #16
+	add	r3, r3, #5570560
+	ldr	sl, [r1, #24]
+	ldr	r8, [r0, #100]
+	add	r5, r5, ip, ror #13
+	add	r3, r3, #21760
+	ldr	ip, [r0, #104]
+	ldr	r7, [r2, #12]
+	add	r5, r5, fp, ror #9
+	ldr	r6, [r0, #40]
+	ldr	fp, [r0, #96]
+	add	r3, r3, #76
+	add	r5, r5, r8, ror #5
+	sub	r3, r3, sl, ror #25
+	eor	ip, ip, ip, lsr #1
+	eor	r3, r3, r7
+	rsb	r6, r6, fp
+	add	r5, r5, ip
+	add	fp, r6, r9
+	add	r5, r5, r3
+	eor	r4, r4, r4, lsr #2
+	ldr	ip, [r0, #56]
+	add	r5, r5, fp
+	add	r5, r5, r4
+	ldr	r3, [r0, #64]
+	str	r5, [r0, #112]
+	ldr	r4, [r0, #72]
+	mov	ip, ip, ror #29
+	ldr	r6, [r0, #80]
+	add	ip, ip, r3, ror #25
+	ldr	r7, [r1, #0]
+	add	ip, ip, r4, ror #19
+	ldr	r3, .L3+4
+	ldr	r4, [r0, #88]
+	ldr	sl, [r1, #52]
+	add	ip, ip, r6, ror #16
+	ldr	r6, [r0, #96]
+	ldr	r9, [r1, #28]
+	add	ip, ip, r4, ror #13
+	add	r3, r3, r7, ror #31
+	ldr	r4, [r0, #108]
+	ldr	r7, [r0, #104]
+	ldr	r8, [r2, #16]
+	add	ip, ip, r6, ror #9
+	add	r3, r3, sl, ror #18
+	ldr	r6, [r0, #44]
+	ldr	sl, [r0, #100]
+	add	ip, ip, r7, ror #5
+	sub	r3, r3, r9, ror #24
+	ldr	r7, [sp, #20]
+	eor	r4, r4, r4, lsr #1
+	rsb	r6, r6, sl
+	eor	r3, r3, r8
+	add	ip, ip, r4
+	add	r9, r6, r7
+	add	ip, ip, r3
+	ldr	r4, [r0, #68]
+	ldr	r3, [r0, #60]
+	eor	r5, r5, r5, lsr #2
+	add	ip, ip, r9
+	add	ip, ip, r5
+	ldr	r6, [r0, #104]
+	mov	r4, r4, ror #25
+	str	ip, [r0, #116]
+	add	r4, r4, r3, ror #29
+	ldr	r5, [r0, #76]
+	add	r4, r4, r6
+	ldr	r7, [r0, #84]
+	ldr	r3, [r1, #4]
+	add	r4, r4, r5, ror #19
+	ldr	r5, [r0, #92]
+	ldr	r8, [r1, #56]
+	add	r4, r4, r7, ror #16
+	add	r4, r4, r5, ror #13
+	ldr	r7, [r0, #108]
+	mov	r3, r3, ror #30
+	add	r4, r4, sl, ror #9
+	add	r3, r3, r8, ror #17
+	ldr	sl, [r1, #32]
+	ldr	r6, [r0, #48]
+	ldr	r5, [r0, #112]
+	add	r4, r4, r7, ror #5
+	sub	r3, r3, #1610612746
+	ldr	r7, [r2, #20]
+	rsb	r4, r6, r4
+	eor	r5, r5, r5, lsr #1
+	sub	r3, r3, sl, ror #23
+	eor	r3, r3, r7
+	add	r4, r4, r5
+	add	r4, r4, r3
+	eor	ip, ip, ip, lsr #2
+	add	r4, r4, fp
+	add	r4, r4, ip
+	str	r4, [r0, #120]
+	ldr	r3, [r0, #72]
+	ldr	r5, [r0, #64]
+	ldr	ip, [r1, #8]
+	ldr	r6, [r0, #108]
+	mov	r3, r3, ror #25
+	ldr	r8, [r1, #60]
+	add	r3, r3, r5, ror #29
+	ldr	r7, [r0, #80]
+	add	r3, r3, r6
+	ldr	r5, [r0, #88]
+	mov	ip, ip, ror #29
+	add	r3, r3, r7, ror #19
+	add	ip, ip, r8, ror #16
+	ldr	r6, [r0, #96]
+	add	r3, r3, r5, ror #16
+	add	ip, ip, #-1526726656
+	ldr	r5, [r0, #104]
+	add	r3, r3, r6, ror #13
+	add	ip, ip, #5570560
+	ldr	r6, [r0, #112]
+	ldr	r8, [r1, #36]
+	add	r3, r3, r5, ror #9
+	add	ip, ip, #21760
+	ldr	r1, [r0, #116]
+	ldr	r5, [r0, #52]
+	ldr	r7, [r2, #24]
+	add	r3, r3, r6, ror #5
+	add	ip, ip, #75
+	rsb	r3, r5, r3
+	sub	ip, ip, r8, ror #22
+	eor	r1, r1, r1, lsr #1
+	add	r3, r3, r1
+	eor	ip, ip, r7
+	add	r3, r3, ip
+	add	r3, r3, r9
+	eor	r4, r4, r4, lsr #2
+	add	r3, r3, r4
+	str	r3, [r0, #124]
+	add	sp, sp, #24
+	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp}
+	bx	lr
+.L4:
+	.align	2
+.L3:
+	.word	1431655760
+	.word	-1700091231
+	.size	bmw_small_f1, .-bmw_small_f1
+	.align	2
+	.global	bmw_small_f0
+	.type	bmw_small_f0, %function
+bmw_small_f0:
+	@ args = 0, pretend = 0, frame = 84
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp}
+	ldr	r3, [r1, #28]
+	ldr	r7, [r2, #28]
+	sub	sp, sp, #84
+	ldr	fp, [r2, #20]
+	ldr	r9, [r2, #40]
+	ldr	sl, [r2, #52]
+	ldr	r4, [r1, #52]
+	eor	r3, r7, r3
+	ldr	r6, [r1, #20]
+	ldr	r5, [r1, #40]
+	ldr	r8, [r2, #56]
+	str	r3, [sp, #76]
+	ldr	ip, [r1, #56]
+	eor	sl, sl, r4
+	eor	r5, r9, r5
+	eor	r6, fp, r6
+	ldr	r4, [sp, #76]
+	ldr	r9, [r2, #32]
+	str	r5, [sp, #72]
+	eor	ip, r8, ip
+	add	r3, r5, r6
+	ldr	r5, [r1, #32]
+	rsb	r8, r4, ip
+	add	r3, r3, sl
+	add	r3, r3, r8
+	eor	r5, r9, r5
+	str	r5, [sp, #56]
+	str	r6, [sp, #68]
+	ldr	r5, [r1, #4]
+	ldr	r6, [r2, #4]
+	str	ip, [sp, #80]
+	mov	ip, r3, lsr #1
+	eor	ip, ip, r3, asl #3
+	eor	r6, r5, r6
+	eor	ip, ip, r3, ror #28
+	str	r6, [sp, #44]
+	eor	ip, ip, r3, ror #13
+	ldr	r7, [r2, #0]
+	ldr	r4, [r1, #0]
+	ldr	r6, [sp, #56]
+	str	ip, [sp, #4]
+	ldr	r3, [sp, #44]
+	ldr	ip, [sp, #72]
+	eor	r7, r7, r4
+	ldr	r5, [r1, #16]
+	add	r4, r6, sl
+	add	r6, ip, r3
+	ldr	ip, [r2, #16]
+	eor	r5, ip, r5
+	ldr	r3, [sp, #4]
+	str	r5, [sp, #48]
+	ldr	r5, [r1, #4]
+	ldr	fp, [r2, #44]
+	add	ip, r3, r5
+	ldr	r3, [r1, #44]
+	eor	fp, fp, r3
+	ldr	r9, [r1, #12]
+	str	fp, [sp, #64]
+	add	r3, r2, #8
+	ldmia	r3, {r3, r5}	@ phole ldm
+	eor	fp, r5, r9
+	ldr	r5, [r1, #8]
+	str	r3, [sp, #40]
+	ldr	r3, [r2, #24]
+	str	r5, [sp, #36]
+	ldr	r5, [r1, #24]
+	str	r3, [sp, #32]
+	ldr	r3, [r2, #36]
+	str	r5, [sp, #28]
+	ldr	r5, [r1, #36]
+	str	r3, [sp, #24]
+	ldr	r3, [r2, #48]
+	ldr	r9, [r2, #60]
+	str	r5, [sp, #20]
+	ldr	r2, [r1, #60]
+	ldr	r5, [r1, #48]
+	add	r4, r4, r7
+	rsb	r4, r6, r4
+	str	r3, [sp, #16]
+	ldr	r3, [sp, #48]
+	str	ip, [r0, #0]
+	str	r5, [sp, #12]
+	str	r2, [sp, #8]
+	ldr	r5, [sp, #64]
+	mov	r2, r4, lsr #2
+	rsb	ip, r7, r3
+	eor	r2, r2, r4, asl #2
+	rsb	r3, r5, sl
+	rsb	ip, fp, ip
+	ldr	r5, [r1, #16]
+	eor	r2, r2, r4, ror #17
+	add	ip, ip, r3
+	eor	r2, r2, r4, ror #3
+	add	r2, r2, r5
+	mov	r3, ip, lsr #1
+	str	r2, [r0, #12]
+	eor	r3, r3, ip, asl #2
+	eor	r3, r3, ip, ror #24
+	ldr	r2, [r1, #28]
+	ldr	r4, [sp, #28]
+	eor	r3, r3, ip, ror #9
+	ldr	ip, [sp, #32]
+	add	r3, r3, r2
+	eor	ip, ip, r4
+	rsb	r2, fp, ip
+	str	ip, [sp, #52]
+	str	r3, [r0, #24]
+	ldr	ip, [sp, #20]
+	ldr	r5, [sp, #24]
+	add	r8, r8, r2
+	eor	r5, r5, ip
+	ldr	r3, [r1, #40]
+	add	r8, r8, r7
+	rsb	r6, r5, r6
+	eor	r8, r8, r8, lsr #1
+	rsb	r6, r2, r6
+	add	r8, r8, r3
+	str	r5, [sp, #60]
+	mov	r2, r6, lsr #2
+	str	r8, [r0, #36]
+	ldr	r3, [sp, #16]
+	ldr	r4, [sp, #12]
+	eor	r2, r2, r6, asl #1
+	eor	r8, r3, r4
+	ldr	r5, [sp, #52]
+	ldr	r3, [r1, #52]
+	ldr	ip, [sp, #60]
+	eor	r2, r2, r6, ror #20
+	eor	r2, r2, r6, ror #7
+	rsb	sl, r5, sl
+	add	r2, r2, r3
+	rsb	r5, ip, r8
+	ldr	r3, [sp, #48]
+	add	r4, sl, r5
+	ldr	r6, [sp, #8]
+	rsb	r4, r3, r4
+	str	r2, [r0, #48]
+	eor	r9, r9, r6
+	mov	r3, r4, lsr #1
+	ldr	r6, [sp, #76]
+	eor	r3, r3, r4, asl #3
+	ldr	r2, [r1, #0]
+	add	ip, r9, r6
+	eor	r3, r3, r4, ror #28
+	eor	r3, r3, r4, ror #13
+	add	ip, ip, r7
+	rsb	ip, r5, ip
+	add	r3, r3, r2
+	str	r3, [r0, #60]
+	ldr	r4, [sp, #36]
+	ldr	r3, [sp, #40]
+	mov	r2, ip, lsr #2
+	eor	r2, r2, ip, asl #1
+	eor	r6, r3, r4
+	eor	r2, r2, ip, ror #20
+	rsb	r5, r6, r9
+	rsb	fp, r8, fp
+	eor	r2, r2, ip, ror #7
+	ldr	ip, [sp, #72]
+	ldr	r3, [r1, #12]
+	add	r4, r5, fp
+	add	r4, r4, ip
+	add	r2, r2, r3
+	mov	r3, r4, lsr #1
+	eor	r3, r3, r4, asl #3
+	eor	r3, r3, r4, ror #28
+	str	r3, [sp, #0]
+	ldr	r3, [sp, #68]
+	str	r2, [r0, #8]
+	rsb	ip, r3, #0
+	ldr	r3, [sp, #0]
+	ldr	r2, [r1, #24]
+	eor	r4, r3, r4, ror #13
+	add	r3, r4, r2
+	add	sl, ip, sl
+	rsb	sl, r5, sl
+	str	r3, [r0, #20]
+	ldr	r5, [sp, #56]
+	ldr	r3, [sp, #68]
+	mov	r2, sl, lsr #2
+	rsb	r4, r3, r5
+	ldr	r5, [sp, #60]
+	eor	r2, r2, sl, asl #2
+	ldr	r3, [r1, #36]
+	rsb	r7, r7, r5
+	eor	r2, r2, sl, ror #17
+	add	r7, r7, r4
+	eor	r2, r2, sl, ror #3
+	rsb	r7, r6, r7
+	add	r2, r2, r3
+	str	r2, [r0, #32]
+	mov	r3, r7, lsr #1
+	eor	r3, r3, r7, asl #2
+	ldr	r2, [r1, #48]
+	eor	r3, r3, r7, ror #24
+	eor	r3, r3, r7, ror #9
+	add	r3, r3, r2
+	ldr	r7, [sp, #64]
+	ldr	r5, [sp, #80]
+	str	r3, [r0, #44]
+	add	r3, r4, fp
+	rsb	r2, r7, r3
+	add	r4, r5, r7
+	ldr	r7, [sp, #56]
+	add	r9, r9, r7
+	ldr	r7, [sp, #52]
+	ldr	r3, [r1, #60]
+	eor	r5, r2, r2, lsr #1
+	add	r2, r4, r7
+	add	r3, r5, r3
+	rsb	r5, r9, r2
+	str	r3, [r0, #56]
+	mov	r3, r5, lsr #1
+	eor	r3, r3, r5, asl #2
+	ldr	r2, [r1, #8]
+	eor	r3, r3, r5, ror #24
+	eor	r3, r3, r5, ror #9
+	add	r3, r3, r2
+	str	r3, [r0, #4]
+	ldr	r3, [sp, #44]
+	ldr	r5, [sp, #60]
+	add	r2, r6, r3
+	ldr	r7, [sp, #80]
+	add	r2, r2, r5
+	rsb	ip, r7, ip
+	rsb	r2, r4, r2
+	ldr	r4, [sp, #48]
+	add	ip, ip, r3
+	rsb	ip, r4, ip
+	ldr	r3, [r1, #20]
+	rsb	ip, r8, ip
+	eor	r2, r2, r2, lsr #1
+	add	r2, r2, r3
+	mov	r3, ip, lsr #2
+	eor	r3, r3, ip, asl #1
+	str	r2, [r0, #16]
+	eor	r3, r3, ip, ror #20
+	ldr	r5, [sp, #76]
+	eor	r3, r3, ip, ror #7
+	ldr	ip, [sp, #44]
+	ldr	r2, [r1, #32]
+	rsb	r9, ip, r9
+	mov	r7, r4
+	add	r4, r5, r4
+	rsb	r9, r4, r9
+	add	r3, r3, r2
+	str	r3, [r0, #28]
+	mov	r2, r9, lsr #1
+	ldr	r3, [sp, #64]
+	eor	r2, r2, r9, asl #3
+	ldr	r5, [sp, #72]
+	add	ip, r3, r6
+	eor	r2, r2, r9, ror #28
+	ldr	r3, [r1, #44]
+	eor	r2, r2, r9, ror #13
+	add	r6, ip, r5
+	add	r6, r6, r4
+	add	r2, r2, r3
+	str	r2, [r0, #40]
+	mov	r3, r6, lsr #2
+	eor	r3, r3, r6, asl #2
+	ldr	r2, [r1, #56]
+	eor	r3, r3, r6, ror #17
+	eor	r3, r3, r6, ror #3
+	add	r3, r3, r2
+	str	r3, [r0, #52]
+	add	sp, sp, #84
+	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp}
+	bx	lr
+	.size	bmw_small_f0, .-bmw_small_f0
+	.align	2
+	.global	bmw224_init
+	.type	bmw224_init, %function
+bmw224_init:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r3, #65536
+	add	r3, r3, #512
+	add	r3, r3, #3
+	str	r3, [r0, #0]
+	mov	r2, r0
+	add	r1, r0, #60
+.L8:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67108864
+	add	r3, r3, #262144
+	add	r3, r3, #1024
+	add	r3, r3, #4
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L8
+	mov	r3, #0
+	str	r3, [r0, #64]
+	bx	lr
+	.size	bmw224_init, .-bmw224_init
+	.align	2
+	.global	bmw256_init
+	.type	bmw256_init, %function
+bmw256_init:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	ldr	r3, .L16
+	str	r3, [r0, #0]
+	mov	r2, r0
+	add	r1, r0, #60
+.L13:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67108864
+	add	r3, r3, #262144
+	add	r3, r3, #1024
+	add	r3, r3, #4
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L13
+	mov	r3, #0
+	str	r3, [r0, #64]
+	bx	lr
+.L17:
+	.align	2
+.L16:
+	.word	1078018627
+	.size	bmw256_init, .-bmw256_init
+	.align	2
+	.global	bmw256_ctx2hash
+	.type	bmw256_ctx2hash, %function
+bmw256_ctx2hash:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	add	r1, r1, #32
+	mov	r2, #32
+	b	memcpy
+	.size	bmw256_ctx2hash, .-bmw256_ctx2hash
+	.align	2
+	.global	bmw224_ctx2hash
+	.type	bmw224_ctx2hash, %function
+bmw224_ctx2hash:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	add	r1, r1, #36
+	mov	r2, #28
+	b	memcpy
+	.size	bmw224_ctx2hash, .-bmw224_ctx2hash
+	.align	2
+	.global	bmw_small_nextBlock
+	.type	bmw_small_nextBlock, %function
+bmw_small_nextBlock:
+	@ args = 0, pretend = 0, frame = 192
+	@ frame_needed = 0, uses_anonymous_args = 0
+	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+	sub	sp, sp, #192
+	mov	r7, r0
+	mov	r8, r1
+	add	r4, sp, #64
+	mov	r0, r4
+	mov	r1, r7
+	mov	r2, r8
+	bl	bmw_small_f0
+	mov	r0, r4
+	mov	r1, r8
+	mov	r2, r7
+	bl	bmw_small_f1
+	add	r1, sp, #128
+	ldmia	r1, {r1, r2, r3, ip}	@ phole ldm
+	str	ip, [sp, #48]
+	ldr	lr, [sp, #168]
+	eor	ip, r1, r2
+	str	r1, [sp, #60]
+	ldr	r1, [sp, #144]
+	str	r2, [sp, #56]
+	ldr	r2, [sp, #172]
+	str	lr, [sp, #28]
+	str	r1, [sp, #44]
+	str	r3, [sp, #52]
+	ldr	r1, [sp, #176]
+	eor	ip, ip, r3
+	ldr	r3, [sp, #48]
+	ldr	fp, [sp, #164]
+	str	r2, [sp, #24]
+	ldr	lr, [sp, #148]
+	ldr	r2, [sp, #28]
+	str	r1, [sp, #20]
+	eor	ip, ip, r3
+	ldr	r1, [sp, #152]
+	ldr	r3, [sp, #44]
+	str	lr, [sp, #40]
+	eor	r0, r2, fp
+	ldr	lr, [sp, #24]
+	ldr	r2, [sp, #180]
+	str	r1, [sp, #36]
+	eor	ip, ip, r3
+	ldr	r1, [sp, #184]
+	ldr	r3, [sp, #40]
+	str	r2, [sp, #16]
+	eor	r0, r0, lr
+	ldr	lr, [sp, #20]
+	eor	ip, ip, r3
+	str	r1, [sp, #12]
+	ldr	r3, [sp, #16]
+	ldr	r1, [sp, #188]
+	eor	r0, r0, lr
+	ldr	r2, [sp, #36]
+	ldr	lr, [sp, #156]
+	eor	r0, r0, r3
+	str	r1, [sp, #8]
+	ldr	r3, [sp, #12]
+	eor	ip, ip, r2
+	eor	r0, r0, r3
+	ldr	r2, [sp, #160]
+	eor	ip, ip, lr
+	ldr	r9, [r8, #0]
+	eor	r0, r0, r1
+	add	r1, sp, #60
+	ldmia	r1, {r1, r3}	@ phole ldm
+	str	r2, [sp, #32]
+	eor	r2, ip, r2
+	eor	r0, r0, r2
+	eor	r9, r9, r1, lsr #5
+	eor	r2, r2, r3
+	eor	r9, r9, r0, asl #5
+	add	r9, r9, r2
+	str	r9, [r7, #0]
+	ldr	r3, [sp, #68]
+	ldr	sl, [r8, #4]
+	ldr	r2, [sp, #56]
+	eor	r3, r3, fp
+	eor	sl, sl, r2, asl #8
+	eor	r3, r3, ip
+	eor	sl, sl, r0, lsr #7
+	add	sl, sl, r3
+	str	sl, [r7, #4]
+	ldr	r3, [sp, #72]
+	ldr	r1, [sp, #28]
+	ldr	r2, [r8, #8]
+	eor	r3, r3, r1
+	ldr	r1, [sp, #52]
+	eor	r2, r2, r1, asl #5
+	eor	r2, r2, r0, lsr #5
+	eor	r3, r3, ip
+	add	r3, r2, r3
+	str	r3, [r7, #8]
+	ldr	r1, [sp, #24]
+	str	r3, [sp, #4]
+	ldr	r3, [sp, #76]
+	ldr	r2, [r8, #12]
+	eor	r3, r3, r1
+	ldr	r1, [sp, #48]
+	eor	r2, r2, r1, asl #5
+	eor	r2, r2, r0, lsr #1
+	eor	r3, r3, ip
+	add	r3, r2, r3
+	str	r3, [r7, #12]
+	ldr	r2, [sp, #20]
+	str	r3, [sp, #0]
+	ldr	r3, [sp, #80]
+	ldr	r1, [r8, #16]
+	eor	r3, r3, r2
+	ldr	r2, [sp, #44]
+	eor	r1, r1, r2
+	eor	r3, r3, ip
+	eor	r1, r1, r0, lsr #3
+	add	r1, r1, r3
+	str	r1, [r7, #16]
+	ldr	r3, [sp, #84]
+	ldr	r2, [sp, #16]
+	ldr	r4, [r8, #20]
+	eor	r3, r3, r2
+	ldr	r2, [sp, #40]
+	eor	r4, r4, r2, lsr #6
+	eor	r3, r3, ip
+	eor	r4, r4, r0, asl #6
+	add	r4, r4, r3
+	str	r4, [r7, #20]
+	ldr	r3, [sp, #36]
+	ldr	r5, [r8, #24]
+	ldr	r2, [sp, #12]
+	eor	r5, r5, r3, asl #6
+	ldr	r3, [sp, #88]
+	eor	r3, r3, r2
+	eor	r3, r3, ip
+	eor	r5, r5, r0, lsr #4
+	add	r5, r5, r3
+	str	r5, [r7, #24]
+	ldr	r6, [r8, #28]
+	ldr	r3, [sp, #92]
+	ldr	r2, [sp, #8]
+	eor	r6, r6, lr, asl #2
+	eor	r3, r3, r2
+	eor	r3, r3, ip
+	eor	r6, r6, r0, lsr #11
+	add	r6, r6, r3
+	str	r6, [r7, #28]
+	ldr	r3, [sp, #96]
+	ldr	r2, [r8, #32]
+	eor	r3, r3, lr
+	ldr	lr, [sp, #32]
+	eor	r3, r3, ip, asl #8
+	eor	r2, r2, lr
+	add	r3, r3, r1, ror #23
+	eor	r2, r2, r0
+	add	r3, r3, r2
+	str	r3, [r7, #32]
+	ldr	r3, [sp, #100]
+	ldr	r1, [sp, #60]
+	ldr	r2, [r8, #36]
+	eor	r3, r3, r1
+	eor	r3, r3, ip, lsr #6
+	eor	r2, r2, fp
+	eor	r2, r2, r0
+	add	r3, r3, r4, ror #22
+	add	r3, r3, r2
+	str	r3, [r7, #36]
+	ldr	r3, [sp, #104]
+	ldr	lr, [sp, #56]
+	ldr	r2, [r8, #40]
+	ldr	r1, [sp, #28]
+	eor	r3, r3, lr
+	eor	r2, r2, r1
+	eor	r3, r3, ip, asl #6
+	eor	r2, r2, r0
+	add	r3, r3, r5, ror #21
+	add	r3, r3, r2
+	str	r3, [r7, #40]
+	ldr	r3, [sp, #108]
+	ldr	lr, [sp, #52]
+	ldr	r2, [r8, #44]
+	ldr	r1, [sp, #24]
+	eor	r3, r3, lr
+	eor	r2, r2, r1
+	eor	r3, r3, ip, asl #4
+	eor	r2, r2, r0
+	add	r3, r3, r6, ror #20
+	add	r3, r3, r2
+	str	r3, [r7, #44]
+	ldr	r3, [sp, #112]
+	ldr	lr, [sp, #48]
+	ldr	r2, [r8, #48]
+	ldr	r1, [sp, #20]
+	eor	r3, r3, lr
+	eor	r2, r2, r1
+	eor	r3, r3, ip, lsr #3
+	eor	r2, r2, r0
+	add	r3, r3, r9, ror #19
+	add	r3, r3, r2
+	str	r3, [r7, #48]
+	ldr	r3, [sp, #116]
+	ldr	lr, [sp, #44]
+	ldr	r2, [r8, #52]
+	ldr	r1, [sp, #16]
+	eor	r3, r3, lr
+	eor	r2, r2, r1
+	eor	r3, r3, ip, lsr #4
+	eor	r2, r2, r0
+	add	r3, r3, sl, ror #18
+	add	r3, r3, r2
+	str	r3, [r7, #52]
+	ldr	lr, [sp, #40]
+	ldr	r3, [sp, #120]
+	ldr	r1, [sp, #12]
+	ldr	r2, [r8, #56]
+	eor	r3, r3, lr
+	ldr	lr, [sp, #4]
+	eor	r2, r2, r1
+	eor	r3, r3, ip, lsr #7
+	add	r3, r3, lr, ror #17
+	eor	r2, r2, r0
+	add	r3, r3, r2
+	str	r3, [r7, #56]
+	ldr	r3, [sp, #124]
+	ldr	r2, [sp, #36]
+	eor	r3, r3, r2
+	ldr	r1, [r8, #60]
+	eor	r3, r3, ip, lsr #2
+	ldr	ip, [sp, #8]
+	ldr	lr, [sp, #0]
+	ldr	r2, [r7, #64]
+	eor	r1, r1, ip
+	add	r3, r3, lr, ror #16
+	eor	r1, r1, r0
+	add	r3, r3, r1
+	add	r2, r2, #1
+	str	r2, [r7, #64]
+	str	r3, [r7, #60]
+	add	sp, sp, #192
+	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+	.size	bmw_small_nextBlock, .-bmw_small_nextBlock
+	.align	2
+	.global	bmw224_nextBlock
+	.type	bmw224_nextBlock, %function
+bmw224_nextBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	b	bmw_small_nextBlock
+	.size	bmw224_nextBlock, .-bmw224_nextBlock
+	.align	2
+	.global	bmw256_nextBlock
+	.type	bmw256_nextBlock, %function
+bmw256_nextBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	b	bmw_small_nextBlock
+	.size	bmw256_nextBlock, .-bmw256_nextBlock
+	.align	2
+	.global	bmw_small_lastBlock
+	.type	bmw_small_lastBlock, %function
+bmw_small_lastBlock:
+	@ args = 0, pretend = 0, frame = 400
+	@ frame_needed = 0, uses_anonymous_args = 0
+	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+	mov	r2, r2, asl #16
+	mov	ip, #508
+	mov	r4, r2, lsr #16
+	add	ip, ip, #3
+	cmp	r4, ip
+	sub	sp, sp, #400
+	mov	fp, r0
+	mov	r8, r1
+	bls	.L29
+	mov	r7, ip
+	mov	r6, r1
+	mov	r5, r4
+.L30:
+	mov	r1, r6
+	mov	r0, fp
+	bl	bmw_small_nextBlock
+	sub	r3, r5, #512
+	mov	r3, r3, asl #16
+	mov	r5, r3, lsr #16
+	cmp	r5, r7
+	add	r6, r6, #64
+	bhi	.L30
+	sub	r2, r4, #512
+	mov	r2, r2, asl #16
+	mov	r3, r2, lsr #25
+	add	r3, r3, #1
+	mov	r2, r2, lsr #16
+	mov	r3, r3, asl #6
+	mov	r4, r2, asl #23
+	add	r8, r8, r3
+	mov	r4, r4, lsr #23
+.L29:
+	add	r9, sp, #336
+	mov	r1, #0
+	mov	r2, #64
+	mov	r0, r9
+	bl	memset
+	add	r2, r4, #7
+	mov	r1, r8
+	mov	r2, r2, asr #3
+	mov	r0, r9
+	bl	memcpy
+	add	r0, sp, #400
+	add	ip, r0, r4, lsr #3
+	ldrb	r2, [ip, #-64]	@ zero_extendqisi2
+	and	r1, r4, #7
+	mov	r3, #128
+	orr	r2, r2, r3, asr r1
+	cmp	r4, #448
+	strb	r2, [ip, #-64]
+	bge	.L37
+	add	r2, sp, #348
+	add	r3, sp, #352
+	add	r7, sp, #356
+	add	r8, sp, #360
+	add	ip, sp, #364
+	str	r2, [sp, #12]
+	str	r3, [sp, #8]
+	str	r7, [sp, #4]
+	str	r8, [sp, #20]
+	str	ip, [sp, #16]
+	ldr	r1, [fp, #64]
+	add	r5, sp, #340
+	add	r6, sp, #344
+.L31:
+	mov	r2, #512
+	mov	r3, r4
+	mov	r4, #0
+	umlal	r3, r4, r2, r1
+	mov	r0, fp
+	mov	r1, r9
+	str	r3, [r9, #56]
+	str	r4, [r9, #60]
+	bl	bmw_small_nextBlock
+	mov	r2, #64
+	mov	r0, r9
+	mov	r1, #170
+	bl	memset
+	mov	r2, #0
+	mov	r3, #160
+.L32:
+	strb	r3, [r9, r2]
+	add	r2, r2, #4
+	add	r3, r3, #1
+	cmp	r2, #64
+	and	r3, r3, #255
+	bne	.L32
+	add	r4, sp, #208
+	mov	r0, r4
+	mov	r1, r9
+	mov	r2, fp
+	bl	bmw_small_f0
+	mov	r0, r4
+	mov	r1, fp
+	mov	r2, r9
+	bl	bmw_small_f1
+	add	r8, sp, #272
+	ldmia	r8, {r8, ip, lr}	@ phole ldm
+	add	r2, sp, #308
+	ldmia	r2, {r2, r3}	@ phole ldm
+	eor	r1, ip, r8
+	str	ip, [sp, #200]
+	ldr	ip, [sp, #292]
+	ldr	r0, [sp, #284]
+	str	r8, [sp, #204]
+	ldr	r8, [sp, #316]
+	ldr	r7, [sp, #288]
+	str	ip, [sp, #184]
+	str	lr, [sp, #196]
+	eor	ip, r3, r2
+	eor	r1, r1, lr
+	ldr	lr, [sp, #320]
+	str	r2, [sp, #172]
+	eor	r1, r1, r0
+	ldr	r2, [sp, #324]
+	eor	ip, ip, r8
+	str	r3, [sp, #168]
+	str	r7, [sp, #188]
+	ldr	r3, [sp, #184]
+	eor	r1, r1, r7
+	eor	ip, ip, lr
+	ldr	r7, [sp, #328]
+	eor	ip, ip, r2
+	eor	r1, r1, r3
+	str	r7, [sp, #152]
+	eor	ip, ip, r7
+	ldr	r3, [fp, #0]
+	ldr	r7, [sp, #204]
+	str	r0, [sp, #192]
+	str	r8, [sp, #164]
+	ldr	r0, [sp, #296]
+	ldr	r8, [sp, #332]
+	str	lr, [sp, #160]
+	add	sl, sp, #300
+	ldmia	sl, {sl, lr}	@ phole ldm
+	eor	r3, r3, r7, lsr #5
+	str	r0, [sp, #180]
+	str	r2, [sp, #156]
+	eor	r1, r1, r0
+	ldr	r2, [fp, #4]
+	str	r8, [sp, #148]
+	str	lr, [sp, #176]
+	eor	ip, ip, r8
+	str	r3, [sp, #144]
+	ldr	r8, [sp, #200]
+	eor	r1, r1, sl
+	eor	r0, r1, lr
+	ldr	r3, [sp, #172]
+	eor	lr, r2, r8, asl #8
+	ldr	r2, [sp, #212]
+	ldr	r7, [sp, #144]
+	eor	r2, r3, r2
+	ldr	r3, [sp, #208]
+	eor	ip, ip, r0
+	eor	r7, r7, ip, asl #5
+	eor	r0, r0, r3
+	eor	r2, r2, r1
+	eor	r3, lr, ip, lsr #7
+	add	r0, r7, r0
+	add	r2, r3, r2
+	str	r0, [r9, #0]
+	str	r2, [r5, #0]
+	ldr	r8, [fp, #8]
+	ldr	r3, [sp, #216]
+	ldr	lr, [sp, #168]
+	str	r0, [sp, #136]
+	ldr	r0, [sp, #196]
+	eor	r3, lr, r3
+	eor	r8, r8, r0, asl #5
+	eor	r3, r3, r1
+	eor	r8, r8, ip, lsr #5
+	add	r8, r8, r3
+	str	r8, [r6, #0]
+	ldr	r7, [fp, #12]
+	ldr	r3, [sp, #220]
+	ldr	r5, [sp, #192]
+	str	r2, [sp, #132]
+	ldr	r2, [sp, #164]
+	eor	r7, r7, r5, asl #5
+	eor	r3, r2, r3
+	eor	r3, r3, r1
+	ldr	lr, [sp, #12]
+	eor	r7, r7, ip, lsr #1
+	add	r7, r7, r3
+	str	r7, [lr, #0]
+	ldr	r6, [fp, #16]
+	ldr	r3, [sp, #224]
+	ldr	r0, [sp, #160]
+	ldr	r2, [sp, #188]
+	eor	r3, r0, r3
+	eor	r6, r2, r6
+	eor	r3, r3, r1
+	eor	r6, r6, ip, lsr #3
+	add	r6, r6, r3
+	ldr	r3, [sp, #8]
+	str	r6, [r3, #0]
+	ldr	r5, [fp, #20]
+	ldr	lr, [sp, #184]
+	ldr	r3, [sp, #228]
+	ldr	r0, [sp, #156]
+	eor	r5, r5, lr, lsr #6
+	eor	r3, r0, r3
+	eor	r3, r3, r1
+	ldr	r2, [sp, #4]
+	eor	r5, r5, ip, asl #6
+	add	r5, r5, r3
+	str	r5, [r2, #0]
+	ldr	lr, [sp, #152]
+	ldr	r0, [sp, #180]
+	ldr	r4, [fp, #24]
+	ldr	r3, [sp, #232]
+	eor	r4, r4, r0, asl #6
+	eor	r3, lr, r3
+	eor	r3, r3, r1
+	eor	r4, r4, ip, lsr #4
+	ldr	r2, [sp, #20]
+	add	r4, r4, r3
+	str	r4, [r2, #0]
+	ldr	r0, [fp, #28]
+	ldr	r3, [sp, #236]
+	ldr	lr, [sp, #148]
+	eor	r0, r0, sl, asl #2
+	eor	r3, lr, r3
+	eor	r3, r3, r1
+	ldr	r2, [sp, #16]
+	eor	r0, r0, ip, lsr #11
+	add	r0, r0, r3
+	str	r0, [r2, #0]
+	ldr	r3, [sp, #240]
+	ldr	r2, [sp, #244]
+	eor	sl, sl, r3
+	ldr	r3, [sp, #204]
+	ldr	lr, [sp, #200]
+	eor	r2, r3, r2
+	ldr	r3, [sp, #248]
+	eor	r3, lr, r3
+	str	r2, [sp, #124]
+	str	r3, [sp, #112]
+	ldr	r2, [sp, #252]
+	ldr	r3, [sp, #196]
+	ldr	lr, [sp, #192]
+	eor	r2, r3, r2
+	ldr	r3, [sp, #256]
+	eor	r3, lr, r3
+	str	r2, [sp, #100]
+	str	r3, [sp, #88]
+	ldr	r2, [sp, #260]
+	ldr	r3, [sp, #188]
+	ldr	lr, [sp, #184]
+	eor	r2, r3, r2
+	ldr	r3, [sp, #264]
+	eor	r3, lr, r3
+	str	r2, [sp, #72]
+	str	r3, [sp, #52]
+	ldr	r2, [sp, #268]
+	ldr	r3, [sp, #180]
+	eor	lr, r3, r2
+	ldr	r3, [fp, #32]
+	ldr	r2, [sp, #176]
+	eor	r2, r2, r3
+	str	r2, [sp, #128]
+	ldr	r3, [fp, #36]
+	ldr	r2, [sp, #172]
+	eor	r2, r2, r3
+	str	r2, [sp, #116]
+	ldr	r3, [fp, #40]
+	ldr	r2, [sp, #168]
+	eor	r2, r2, r3
+	str	r2, [sp, #104]
+	ldr	r3, [fp, #44]
+	ldr	r2, [sp, #164]
+	eor	r2, r2, r3
+	str	r2, [sp, #92]
+	ldr	r3, [fp, #48]
+	ldr	r2, [sp, #160]
+	eor	r2, r2, r3
+	str	r2, [sp, #76]
+	ldr	r3, [fp, #52]
+	ldr	r2, [sp, #156]
+	eor	r2, r2, r3
+	str	r2, [sp, #60]
+	ldr	r3, [fp, #56]
+	ldr	r2, [sp, #152]
+	eor	lr, lr, r1, lsr #2
+	eor	r2, r2, r3
+	str	r2, [sp, #44]
+	str	lr, [sp, #36]
+	ldr	r2, [fp, #60]
+	ldr	lr, [sp, #148]
+	ldr	r3, [sp, #124]
+	eor	lr, lr, r2
+	ldr	r2, [sp, #112]
+	str	lr, [sp, #28]
+	eor	lr, r3, r1, lsr #6
+	ldr	r3, [sp, #100]
+	eor	r2, r2, r1, asl #6
+	str	r2, [sp, #0]
+	eor	r2, r3, r1, asl #4
+	ldr	r3, [sp, #88]
+	eor	r3, r3, r1, lsr #3
+	str	r3, [sp, #84]
+	ldr	r3, [sp, #72]
+	eor	r3, r3, r1, lsr #4
+	str	r3, [sp, #68]
+	ldr	r3, [sp, #52]
+	add	lr, lr, r5, ror #22
+	add	r2, r2, r0, ror #20
+	ldr	r5, [sp, #0]
+	ldr	r0, [sp, #136]
+	eor	sl, sl, r1, asl #8
+	str	lr, [sp, #120]
+	eor	r1, r3, r1, lsr #7
+	str	r2, [sp, #96]
+	ldr	r3, [sp, #132]
+	ldr	lr, [sp, #84]
+	ldr	r2, [sp, #68]
+	add	r4, r5, r4, ror #21
+	add	lr, lr, r0, ror #19
+	add	r2, r2, r3, ror #18
+	str	r4, [sp, #108]
+	str	lr, [sp, #80]
+	str	r2, [sp, #64]
+	ldr	r5, [sp, #36]
+	add	r7, r5, r7, ror #16
+	str	r7, [sp, #32]
+	ldr	r7, [sp, #28]
+	add	r1, r1, r8, ror #17
+	ldr	r0, [sp, #116]
+	ldr	r8, [sp, #128]
+	ldr	r2, [sp, #104]
+	ldr	r3, [sp, #92]
+	eor	r7, r7, ip
+	str	r7, [sp, #24]
+	eor	lr, r8, ip
+	eor	r5, r0, ip
+	eor	r8, r3, ip
+	eor	r7, r2, ip
+	ldr	r0, [sp, #76]
+	ldr	r3, [sp, #44]
+	ldr	r2, [sp, #60]
+	add	sl, sl, r6, ror #23
+	eor	r2, r2, ip
+	eor	r6, r0, ip
+	add	sl, sl, lr
+	eor	ip, r3, ip
+	ldr	lr, [sp, #108]
+	str	ip, [sp, #40]
+	str	r1, [sp, #48]
+	str	r2, [sp, #56]
+	ldr	ip, [sp, #120]
+	add	r7, lr, r7
+	mov	r4, r9
+	ldmia	r4!, {r0, r1, r2, r3}
+	str	r7, [r9, #40]
+	ldr	r7, [sp, #96]
+	add	r5, ip, r5
+	ldr	lr, [sp, #56]
+	ldr	ip, [sp, #64]
+	str	r5, [r9, #36]
+	add	r5, r7, r8
+	ldr	r8, [sp, #80]
+	add	r7, r8, r6
+	add	r6, ip, lr
+	ldr	ip, [sp, #48]
+	ldr	lr, [sp, #40]
+	add	r8, ip, lr
+	ldr	ip, [sp, #32]
+	ldr	lr, [sp, #24]
+	add	ip, ip, lr
+	str	ip, [r9, #60]
+	mov	ip, fp
+	str	sl, [r9, #32]
+	str	r5, [r9, #44]
+	str	r7, [r9, #48]
+	str	r6, [r9, #52]
+	str	r8, [r9, #56]
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	add	sp, sp, #400
+	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+.L37:
+	mov	r0, fp
+	mov	r1, r9
+	bl	bmw_small_nextBlock
+	ldr	r1, [fp, #64]
+	mov	r3, #0
+	str	r3, [sp, #388]
+	str	r3, [sp, #336]
+	str	r3, [sp, #340]
+	str	r3, [sp, #344]
+	str	r3, [sp, #348]
+	str	r3, [sp, #352]
+	str	r3, [sp, #356]
+	str	r3, [sp, #360]
+	str	r3, [sp, #364]
+	str	r3, [sp, #368]
+	str	r3, [sp, #372]
+	str	r3, [sp, #376]
+	str	r3, [sp, #380]
+	str	r3, [sp, #384]
+	sub	r1, r1, #1
+	add	lr, sp, #348
+	add	r0, sp, #352
+	add	r2, sp, #356
+	add	r3, sp, #360
+	add	r7, sp, #364
+	str	r1, [fp, #64]
+	add	r5, sp, #340
+	add	r6, sp, #344
+	str	lr, [sp, #12]
+	str	r0, [sp, #8]
+	str	r2, [sp, #4]
+	str	r3, [sp, #20]
+	str	r7, [sp, #16]
+	b	.L31
+	.size	bmw_small_lastBlock, .-bmw_small_lastBlock
+	.align	2
+	.global	bmw256_lastBlock
+	.type	bmw256_lastBlock, %function
+bmw256_lastBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r2, r2, asl #16
+	mov	r2, r2, lsr #16
+	b	bmw_small_lastBlock
+	.size	bmw256_lastBlock, .-bmw256_lastBlock
+	.align	2
+	.global	bmw224_lastBlock
+	.type	bmw224_lastBlock, %function
+bmw224_lastBlock:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 0, uses_anonymous_args = 0
+	@ link register save eliminated.
+	mov	r2, r2, asl #16
+	mov	r2, r2, lsr #16
+	b	bmw_small_lastBlock
+	.size	bmw224_lastBlock, .-bmw224_lastBlock
+	.align	2
+	.global	bmw256
+	.type	bmw256, %function
+bmw256:
+	@ args = 0, pretend = 0, frame = 68
+	@ frame_needed = 0, uses_anonymous_args = 0
+	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+	ldr	r3, .L49
+	sub	sp, sp, #68
+	add	r6, sp, #68
+	str	r3, [r6, #-68]!
+	mov	sl, r1
+	mov	r7, r2
+	mov	r9, r0
+	mov	r2, sp
+	add	r1, sp, #60
+.L43:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67108864
+	add	r3, r3, #262144
+	add	r3, r3, #1024
+	add	r3, r3, #4
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L43
+	mov	r2, #508
+	add	r2, r2, #3
+	mov	r3, #0
+	cmp	r7, r2
+	str	r3, [sp, #64]
+	bls	.L44
+	mov	r8, r2
+	mov	r5, sl
+	mov	r4, r7
+.L45:
+	mov	r1, r5
+	sub	r4, r4, #512
+	mov	r0, sp
+	bl	bmw_small_nextBlock
+	cmp	r4, r8
+	add	r5, r5, #64
+	bhi	.L45
+	sub	r2, r7, #512
+	mov	r3, r2, lsr #9
+	add	r3, r3, #1
+	mov	r3, r3, asl #6
+	mov	r7, r2, asl #23
+	add	sl, sl, r3
+	mov	r7, r7, lsr #23
+.L44:
+	mov	r2, r7, asl #16
+	mov	r1, sl
+	mov	r0, sp
+	mov	r2, r2, lsr #16
+	bl	bmw_small_lastBlock
+	mov	r0, r9
+	add	r1, sp, #32
+	mov	r2, #32
+	bl	memcpy
+	add	sp, sp, #68
+	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+.L50:
+	.align	2
+.L49:
+	.word	1078018627
+	.size	bmw256, .-bmw256
+	.align	2
+	.global	bmw224
+	.type	bmw224, %function
+bmw224:
+	@ args = 0, pretend = 0, frame = 68
+	@ frame_needed = 0, uses_anonymous_args = 0
+	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+	mov	r3, #65536
+	sub	sp, sp, #68
+	add	r3, r3, #512
+	add	r3, r3, #3
+	add	r6, sp, #68
+	str	r3, [r6, #-68]!
+	mov	sl, r1
+	mov	r7, r2
+	mov	r9, r0
+	mov	r2, sp
+	add	r1, sp, #60
+.L52:
+	ldr	r3, [r2, #0]
+	add	r3, r3, #67108864
+	add	r3, r3, #262144
+	add	r3, r3, #1024
+	add	r3, r3, #4
+	str	r3, [r2, #4]!
+	cmp	r2, r1
+	bne	.L52
+	mov	r2, #508
+	add	r2, r2, #3
+	mov	r3, #0
+	cmp	r7, r2
+	str	r3, [sp, #64]
+	bls	.L53
+	mov	r8, r2
+	mov	r5, sl
+	mov	r4, r7
+.L54:
+	mov	r1, r5
+	sub	r4, r4, #512
+	mov	r0, sp
+	bl	bmw_small_nextBlock
+	cmp	r4, r8
+	add	r5, r5, #64
+	bhi	.L54
+	sub	r2, r7, #512
+	mov	r3, r2, lsr #9
+	add	r3, r3, #1
+	mov	r3, r3, asl #6
+	mov	r7, r2, asl #23
+	add	sl, sl, r3
+	mov	r7, r7, lsr #23
+.L53:
+	mov	r2, r7, asl #16
+	mov	r1, sl
+	mov	r0, sp
+	mov	r2, r2, lsr #16
+	bl	bmw_small_lastBlock
+	mov	r0, r9
+	add	r1, sp, #36
+	mov	r2, #28
+	bl	memcpy
+	add	sp, sp, #68
+	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+	.size	bmw224, .-bmw224
+	.ident	"GCC: (GNU) 4.3.2"
diff --git a/bmw/bmw_small_speed_asm_f0.S b/bmw/bmw_small_speed_asm_f0.S
new file mode 100644
index 0000000..001eafa
--- /dev/null
+++ b/bmw/bmw_small_speed_asm_f0.S
@@ -0,0 +1,118 @@
+/* bmw_small_speed_asm_f0.S */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+	.syntax unified
+
+.macro S32_0 out:req in:req
+	lsr \out, \in, #1
+	eor \out, \out, \in, LSL #3
+	eor \out, \out, \in, ROR #28
+	eor \out, \out, \in, ROR #13
+.endm
+
+.macro S32_1 out:req in:req
+	lsr \out, \in, #1
+	eor \out, \out, \in, LSL #2
+	eor \out, \out, \in, ROR #24
+	eor \out, \out, \in, ROR #9
+.endm
+
+.macro S32_2 out:req in:req
+	lsr \out, \in, #2
+	eor \out, \out, \in, LSL #1
+	eor \out, \out, \in, ROR #20
+	eor \out, \out, \in, ROR #7
+.endm
+
+.macro S32_3 out:req in:req
+	lsr \out, \in, #2
+	eor \out, \out, \in, LSL #2
+	eor \out, \out, \in, ROR #17
+	eor \out, \out, \in, ROR #3
+.endm
+
+.macro S32_4 in:req
+	eor \in, \in, \in, LSR #1
+.endm
+
+.macro S32_5 in:req
+	eor \in, \in, \in, LSR #2
+.endm
+
+#define T00_ADDR [SP, #(15-3)*4]
+#define T01_ADDR [SP, #(15-2)*4]
+#define T02_ADDR [SP, #(15-1)*4]
+#define T03_ADDR [SP, #(15-0)*4]
+#define T04_ADDR [SP, #(15-7)*4]
+#define T05_ADDR [SP, #(15-6)*4]
+#define T06_ADDR [SP, #(15-5)*4]
+#define T07_ADDR [SP, #(15-4)*4]
+#define T08_ADDR [SP, #(15-11)*4]
+#define T09_ADDR [SP, #(15-10)*4]
+#define T10_ADDR [SP, #(15-9)*4]
+#define T11_ADDR [SP, #(15-8)*4]
+#define T12_ADDR [SP, #(15-15)*4]
+#define T13_ADDR [SP, #(15-14)*4]
+#define T14_ADDR [SP, #(15-13)*4]
+#define T15_ADDR [SP, #(15-12)*4]
+
+	.text
+	.align 2
+	.thumb
+	.thumb_func
+	.type	bmw_small_f0, %function
+	.global bmw_small_f0
+bmw_small_f0:
+	push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
+	/* memxor(<STACK>, h, m, 16) */
+	ldmia r1!, {r4, r5, r6, r7}
+	ldmia r2!, {r8, r9, r10, r11}
+	eor r4, r8
+	eor r5, r9
+	eor r6, r10
+	eor r7, r11
+	push {r4, r5, r6, r7}
+	ldmia r1!, {r4, r5, r6, r7}
+	ldmia r2!, {r8, r9, r10, r11}
+	eor r4, r8
+	eor r5, r9
+	eor r6, r10
+	eor r7, r11
+	push {r4, r5, r6, r7}
+	ldmia r1!, {r4, r5, r6, r7}
+	ldmia r2!, {r8, r9, r10, r11}
+	eor r4, r8
+	eor r5, r9
+	eor r6, r10
+	eor r7, r11
+	push {r4, r5, r6, r7}
+	ldmia r1!, {r4, r5, r6, r7}
+	ldmia r2!, {r8, r9, r10, r11}
+	eor r4, r8
+	eor r5, r9
+	eor r6, r10
+	eor r7, r11
+	push {r4, r5, r6, r7}
+    sub r1, #16*4
+
+#include "f0_small_autogen.i"
+
+	add SP, #16*4
+	pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, PC}
+
diff --git a/bmw/bmw_small_speed_asmmix_f0.S b/bmw/bmw_small_speed_asmmix_f0.S
new file mode 100644
index 0000000..8225271
--- /dev/null
+++ b/bmw/bmw_small_speed_asmmix_f0.S
@@ -0,0 +1,71 @@
+/* bmw_small_speed_asm_f0.S */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+	.syntax unified
+
+.macro S32_0 out:req in:req
+	lsr \out, \in, #1
+	eor \out, \out, \in, LSL #3
+	eor \out, \out, \in, ROR #28
+	eor \out, \out, \in, ROR #13
+.endm
+
+.macro S32_1 out:req in:req
+	lsr \out, \in, #1
+	eor \out, \out, \in, LSL #2
+	eor \out, \out, \in, ROR #24
+	eor \out, \out, \in, ROR #9
+.endm
+
+.macro S32_2 out:req in:req
+	lsr \out, \in, #2
+	eor \out, \out, \in, LSL #1
+	eor \out, \out, \in, ROR #20
+	eor \out, \out, \in, ROR #7
+.endm
+
+.macro S32_3 out:req in:req
+	lsr \out, \in, #2
+	eor \out, \out, \in, LSL #2
+	eor \out, \out, \in, ROR #17
+	eor \out, \out, \in, ROR #3
+.endm
+
+.macro S32_4 in:req
+	eor \in, \in, \in, LSR #1
+.endm
+
+.macro S32_5 in:req
+	eor \in, \in, \in, LSR #2
+.endm
+
+
+	.text
+	.align 2
+	.thumb
+	.thumb_func
+	.type	bmw_small_f0, %function
+	.global bmw_small_f0
+bmw_small_f0:
+	push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
+
+#include "f0_small_autogen_mix.i"
+
+	pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, PC}
+
diff --git a/bmw/bmw_small_speed_cstub.c b/bmw/bmw_small_speed_cstub.c
new file mode 100644
index 0000000..b455bc2
--- /dev/null
+++ b/bmw/bmw_small_speed_cstub.c
@@ -0,0 +1,339 @@
+/* bmw_small.c */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+ * \file    bmw_small.c
+ * \author  Daniel Otte
+ * \email   daniel.otte@rub.de
+ * \date    2009-04-27
+ * \license GPLv3 or later
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "bmw_small.h"
+
+#define SHL32(a,n) ((a)<<(n))
+#define SHR32(a,n) ((a)>>(n))
+#define ROTL32(a,n) (((a)<<(n))|((a)>>(32-(n))))
+#define ROTR32(a,n) (((a)>>(n))|((a)<<(32-(n))))
+
+
+#define DEBUG 0
+
+
+#if DEBUG
+ #include "cli.h"
+
+ void ctx_dump(const bmw_small_ctx_t* ctx){
+ 	uint8_t i;
+	cli_putstr("\r\n==== ctx dump ====");
+	for(i=0; i<16;++i){
+		cli_putstr("\r\n h[");
+		cli_hexdump(&i, 1);
+		cli_putstr("] = ");
+		cli_hexdump_rev(&(ctx->h[i]), 4);
+	}
+	cli_putstr("\r\n counter = ");
+	cli_hexdump(&(ctx->counter), 4);
+ }
+
+ void dump_x(const uint32_t* q, uint8_t elements, char x){
+	uint8_t i;
+ 	cli_putstr("\r\n==== ");
+	cli_putc(x);
+	cli_putstr(" dump ====");
+	for(i=0; i<elements;++i){
+		cli_putstr("\r\n ");
+		cli_putc(x);
+		cli_putstr("[");
+		cli_hexdump(&i, 1);
+		cli_putstr("] = ");
+		cli_hexdump_rev(&(q[i]), 4);
+	}
+ }
+#else
+ #define ctx_dump(x)
+ #define dump_x(a,b,c)
+#endif
+
+#define S32_0(x) ( (SHR32((x),   1)) ^ \
+	               (SHL32((x),   3)) ^ \
+	               (ROTL32((x),  4)) ^ \
+	               (ROTR32((x), 13)) )
+
+#define S32_1(x) ( (SHR32((x),   1)) ^ \
+	               (SHL32((x),   2)) ^ \
+	               (ROTL32((x),  8)) ^ \
+	               (ROTR32((x),  9)) )
+
+#define S32_2(x) ( (SHR32((x),   2)) ^ \
+	               (SHL32((x),   1)) ^ \
+	               (ROTL32((x), 12)) ^ \
+	               (ROTR32((x),  7)) )
+
+#define S32_3(x) ( (SHR32((x),   2)) ^ \
+	               (SHL32((x),   2)) ^ \
+	               (ROTL32((x), 15)) ^ \
+	               (ROTR32((x),  3)) )
+
+#define S32_4(x) ( (SHR32((x),   1)) ^ (x))
+
+#define S32_5(x) ( (SHR32((x),   2)) ^ (x))
+
+#define R32_1(x)   (ROTL32((x),  3))
+#define R32_2(x)   (ROTL32((x),  7))
+#define R32_3(x)   (ROTL32((x), 13))
+#define R32_4(x)   (ROTL32((x), 16))
+#define R32_5(x)   (ROTR32((x), 13))
+#define R32_6(x)   (ROTR32((x),  9))
+#define R32_7(x)   (ROTR32((x),  5))
+
+
+#include "f1_autogen.i"
+
+void bmw_small_f0(uint32_t* q, uint32_t* h, const uint32_t* m);
+
+#if 0
+static inline
+void bmw_small_f0(uint32_t* q, uint32_t* h, const uint32_t* m){
+	uint32_t t[16];
+	uint32_t tr0, tr1, tr2, tmp;
+	t[ 0] = h[ 0] ^ m[ 0];
+	t[ 1] = h[ 1] ^ m[ 1];
+	t[ 2] = h[ 2] ^ m[ 2];
+	t[ 3] = h[ 3] ^ m[ 3];
+	t[ 4] = h[ 4] ^ m[ 4];
+	t[ 6] = h[ 6] ^ m[ 6];
+	t[ 8] = h[ 8] ^ m[ 8];
+	t[ 9] = h[ 9] ^ m[ 9];
+	t[11] = h[11] ^ m[11];
+	t[12] = h[12] ^ m[12];
+	t[15] = h[15] ^ m[15];
+	t[ 5] = h[ 5] ^ m[ 5];
+	t[10] = h[10] ^ m[10];
+	t[13] = h[13] ^ m[13];
+	t[ 7] = h[ 7] ^ m[ 7];
+	t[14] = h[14] ^ m[14];
+
+	dump_x(t, 16, 'T');
+	/*
+	q[ 0] = (t[ 5] - t[ 7] + t[10] + t[13] + t[14]);
+	q[ 3] = (t[ 0] - t[ 1] + t[ 8] - t[10] + t[13]);
+	q[ 6] = (t[ 4] - t[ 0] - t[ 3] - t[11] + t[13]);
+	q[ 9] = (t[ 0] - t[ 3] + t[ 6] - t[ 7] + t[14]);
+	q[12] = (t[ 1] + t[ 3] - t[ 6] - t[ 9] + t[10]);
+	q[15] = (t[12] - t[ 4] - t[ 6] - t[ 9] + t[13]);
+	q[ 2] = (t[ 0] + t[ 7] + t[ 9] - t[12] + t[15]);
+	q[ 5] = (t[ 3] - t[ 2] + t[10] - t[12] + t[15]);
+	q[ 8] = (t[ 2] - t[ 5] - t[ 6] + t[13] - t[15]);
+	q[11] = (t[ 8] - t[ 0] - t[ 2] - t[ 5] + t[ 9]);
+	q[14] = (t[ 3] - t[ 5] + t[ 8] - t[11] - t[12]);
+	q[ 1] = (t[ 6] - t[ 8] + t[11] + t[14] - t[15]);
+	q[ 4] = (t[ 1] + t[ 2] + t[ 9] - t[11] - t[14]);
+	q[ 7] = (t[ 1] - t[ 4] - t[ 5] - t[12] - t[14]);
+	q[10] = (t[ 8] - t[ 1] - t[ 4] - t[ 7] + t[15]);
+	q[13] = (t[ 2] + t[ 4] + t[ 7] + t[10] + t[11]);
+	*/
+	tmp = +t[ 5] +t[10] +t[13] +(tr1=-t[ 7]+t[14]) ;
+	q[ 0] = S32_0(tmp) + h[ 1];
+	tmp = +t[ 8] +t[13] +t[ 0] -(tr2=+t[ 1]+t[10]) ;
+	q[ 3] = S32_3(tmp) + h[ 4];
+	tmp = -t[11] +t[13] -t[ 0] -t[ 3] +t[ 4] ;
+	q[ 6] = S32_1(tmp) + h[ 7];
+	tmp = +t[ 0] +(tr0=-t[ 3]+t[ 6]) +(tr1) ;
+	q[ 9] = S32_4(tmp) + h[10];
+	tmp = -t[ 9] -(tr0) +(tr2) ;
+	q[12] = S32_2(tmp) + h[13];
+	tmp = -t[ 4] +(tr0=-t[ 9]+t[12]) +(tr1=-t[ 6]+t[13]) ;
+	q[15] = S32_0(tmp) + h[ 0];
+	tmp = +t[ 7] +t[15] +t[ 0] -(tr0) ;
+	q[ 2] = S32_2(tmp) + h[ 3];
+	tmp = +t[10] +(tr0=-t[ 2]+t[15]) +(tr2=+t[ 3]-t[12]) ;
+	q[ 5] = S32_0(tmp) + h[ 6];
+	tmp = -t[ 5] -(tr0) +(tr1) ;
+	q[ 8] = S32_3(tmp) + h[ 9];
+	tmp = -t[ 0] -t[ 2] +t[ 9] +(tr0=-t[ 5]+t[ 8]) ;
+	q[11] = S32_1(tmp) + h[12];
+	tmp = -t[11] +(tr0) +(tr2) ;
+	q[14] = S32_4(tmp) + h[15];
+	tmp = +t[ 6] +(tr0=+t[11]+t[14]) -(tr1=+t[ 8]+t[15]) ;
+	q[ 1] = S32_1(tmp) + h[ 2];
+	tmp = +t[ 9] +t[ 1] +t[ 2] -(tr0) ;
+	q[ 4] = S32_4(tmp) + h[ 5];
+	tmp = -t[12] -t[14] +t[ 1] -t[ 4] -t[ 5] ;
+	q[ 7] = S32_2(tmp) + h[ 8];
+	tmp = -t[ 1] -(tr0=+t[ 4]+t[ 7]) +(tr1) ;
+	q[10] = S32_0(tmp) + h[11];
+	tmp = +t[ 2] +t[10] +t[11] +(tr0) ;
+	q[13] = S32_3(tmp) + h[14];
+
+	dump_x(q, 16, 'W');
+}
+#endif
+
+static inline
+void bmw_small_f2(uint32_t* h, uint32_t* q, const uint32_t* m){
+	uint32_t xl, xh;
+	xl =      q[16] ^ q[17] ^ q[18] ^ q[19] ^ q[20] ^ q[21] ^ q[22] ^ q[23];
+	xh = xl ^ q[24] ^ q[25] ^ q[26] ^ q[27] ^ q[28] ^ q[29] ^ q[30] ^ q[31];
+#if DEBUG
+	cli_putstr("\r\n XL = ");
+	cli_hexdump_rev(&xl, 4);
+	cli_putstr("\r\n XH = ");
+	cli_hexdump_rev(&xh, 4);
+#endif
+
+	h[0] = (SHL32(xh, 5) ^ SHR32(q[16], 5) ^ m[ 0]) + (xl ^ q[24] ^ q[ 0]);
+	h[1] = (SHR32(xh, 7) ^ SHL32(q[17], 8) ^ m[ 1]) + (xl ^ q[25] ^ q[ 1]);
+	h[2] = (SHR32(xh, 5) ^ SHL32(q[18], 5) ^ m[ 2]) + (xl ^ q[26] ^ q[ 2]);
+	h[3] = (SHR32(xh, 1) ^ SHL32(q[19], 5) ^ m[ 3]) + (xl ^ q[27] ^ q[ 3]);
+	h[4] = (SHR32(xh, 3) ^ q[20]           ^ m[ 4]) + (xl ^ q[28] ^ q[ 4]);
+	h[5] = (SHL32(xh, 6) ^ SHR32(q[21], 6) ^ m[ 5]) + (xl ^ q[29] ^ q[ 5]);
+	h[6] = (SHR32(xh, 4) ^ SHL32(q[22], 6) ^ m[ 6]) + (xl ^ q[30] ^ q[ 6]);
+	h[7] = (SHR32(xh,11) ^ SHL32(q[23], 2) ^ m[ 7]) + (xl ^ q[31] ^ q[ 7]);
+
+	h[ 8] = ROTL32(h[4],  9) + (xh ^ q[24] ^ m[ 8]) + (SHL32(xl, 8) ^ q[23] ^ q[ 8]);
+	h[ 9] = ROTL32(h[5], 10) + (xh ^ q[25] ^ m[ 9]) + (SHR32(xl, 6) ^ q[16] ^ q[ 9]);
+	h[10] = ROTL32(h[6], 11) + (xh ^ q[26] ^ m[10]) + (SHL32(xl, 6) ^ q[17] ^ q[10]);
+	h[11] = ROTL32(h[7], 12) + (xh ^ q[27] ^ m[11]) + (SHL32(xl, 4) ^ q[18] ^ q[11]);
+	h[12] = ROTL32(h[0], 13) + (xh ^ q[28] ^ m[12]) + (SHR32(xl, 3) ^ q[19] ^ q[12]);
+	h[13] = ROTL32(h[1], 14) + (xh ^ q[29] ^ m[13]) + (SHR32(xl, 4) ^ q[20] ^ q[13]);
+	h[14] = ROTL32(h[2], 15) + (xh ^ q[30] ^ m[14]) + (SHR32(xl, 7) ^ q[21] ^ q[14]);
+	h[15] = ROTL32(h[3], 16) + (xh ^ q[31] ^ m[15]) + (SHR32(xl, 2) ^ q[22] ^ q[15]);
+}
+
+void bmw_small_nextBlock(bmw_small_ctx_t* ctx, const void* block){
+	uint32_t q[32];
+	dump_x(block, 16, 'M');
+	bmw_small_f0(q, ctx->h, block);
+	dump_x(q, 16, 'Q');
+	bmw_small_f1(q, block, ctx->h);
+	dump_x(q+16, 16, 'Q');
+	bmw_small_f2(ctx->h, q, block);
+	ctx->counter += 1;
+	ctx_dump(ctx);
+}
+
+void bmw_small_lastBlock(bmw_small_ctx_t* ctx, const void* block, uint16_t length_b){
+	union {
+		uint8_t   v8[64];
+		uint32_t v32[16];
+		uint64_t v64[ 8];
+	} buffer;
+	while(length_b >= BMW_SMALL_BLOCKSIZE){
+		bmw_small_nextBlock(ctx, block);
+		length_b -= BMW_SMALL_BLOCKSIZE;
+		block = (uint8_t*)block + BMW_SMALL_BLOCKSIZE_B;
+	}
+	memset(buffer.v8, 0, 64);
+	memcpy(buffer.v8, block, (length_b+7)/8);
+	buffer.v8[length_b>>3] |= 0x80 >> (length_b&0x07);
+	if(length_b+1>64*8-64){
+		bmw_small_nextBlock(ctx, buffer.v8);
+		memset(buffer.v8, 0, 64-8);
+		ctx->counter -= 1;
+	}
+	buffer.v64[7] = (uint64_t)(ctx->counter*512LL)+(uint64_t)length_b;
+	bmw_small_nextBlock(ctx, buffer.v8);
+	uint8_t i;
+	uint32_t q[32];
+	memset(buffer.v8, 0xaa, 64);
+	for(i=0; i<16;++i){
+		buffer.v8[i*4] = i+0xa0;
+	}
+//	dump_x(buffer.v8, 16, 'A');
+	dump_x(ctx->h, 16, 'M');
+	bmw_small_f0(q, buffer.v32, ctx->h);
+	dump_x(buffer.v8, 16, 'a');
+	dump_x(q, 16, 'Q');
+	bmw_small_f1(q, ctx->h, buffer.v32);
+	dump_x(q, 32, 'Q');
+	bmw_small_f2(buffer.v32, q, ctx->h);
+	memcpy(ctx->h, buffer.v8, 64);
+}
+
+void bmw224_init(bmw224_ctx_t* ctx){
+	uint8_t i;
+	ctx->h[0] = 0x00010203;
+	for(i=1; i<16; ++i){
+		ctx->h[i] = ctx->h[i-1]+ 0x04040404;
+	}
+	ctx->counter=0;
+	ctx_dump(ctx);
+}
+
+void bmw256_init(bmw256_ctx_t* ctx){
+	uint8_t i;
+	ctx->h[0] = 0x40414243;
+	for(i=1; i<16; ++i){
+		ctx->h[i] = ctx->h[i-1]+ 0x04040404;
+	}
+	ctx->counter=0;
+	ctx_dump(ctx);
+}
+
+void bmw224_nextBlock(bmw224_ctx_t* ctx, const void* block){
+	bmw_small_nextBlock(ctx, block);
+}
+
+void bmw256_nextBlock(bmw256_ctx_t* ctx, const void* block){
+	bmw_small_nextBlock(ctx, block);
+}
+
+void bmw224_lastBlock(bmw224_ctx_t* ctx, const void* block, uint16_t length_b){
+	bmw_small_lastBlock(ctx, block, length_b);
+}
+
+void bmw256_lastBlock(bmw256_ctx_t* ctx, const void* block, uint16_t length_b){
+	bmw_small_lastBlock(ctx, block, length_b);
+}
+
+void bmw224_ctx2hash(void* dest, const bmw224_ctx_t* ctx){
+	memcpy(dest, &(ctx->h[9]), 224/8);
+}
+
+void bmw256_ctx2hash(void* dest, const bmw256_ctx_t* ctx){
+	memcpy(dest, &(ctx->h[8]), 256/8);
+}
+
+void bmw224(void* dest, const void* msg, uint32_t length_b){
+	bmw_small_ctx_t ctx;
+	bmw224_init(&ctx);
+	while(length_b>=BMW_SMALL_BLOCKSIZE){
+		bmw_small_nextBlock(&ctx, msg);
+		length_b -= BMW_SMALL_BLOCKSIZE;
+		msg = (uint8_t*)msg + BMW_SMALL_BLOCKSIZE_B;
+	}
+	bmw_small_lastBlock(&ctx, msg, length_b);
+	bmw224_ctx2hash(dest, &ctx);
+}
+
+void bmw256(void* dest, const void* msg, uint32_t length_b){
+	bmw_small_ctx_t ctx;
+	bmw256_init(&ctx);
+	while(length_b>=BMW_SMALL_BLOCKSIZE){
+		bmw_small_nextBlock(&ctx, msg);
+		length_b -= BMW_SMALL_BLOCKSIZE;
+		msg = (uint8_t*)msg + BMW_SMALL_BLOCKSIZE_B;
+	}
+	bmw_small_lastBlock(&ctx, msg, length_b);
+	bmw256_ctx2hash(dest, &ctx);
+}
+
diff --git a/bmw/bmw_small_speed_neon.s b/bmw/bmw_small_speed_neon.s
new file mode 100644
index 0000000..a382a3a
--- /dev/null
+++ b/bmw/bmw_small_speed_neon.s
@@ -0,0 +1,17268 @@
+	.cpu cortex-a8
+	.eabi_attribute 27, 3
+	.fpu neon
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.eabi_attribute 18, 4
+	.file	"bmw_small_speed_neon.c"
+	.text
+	.align	2
+	.type	bmw_small_f1, %function
+bmw_small_f1:
+	@ args = 0, pretend = 0, frame = 13368
+	@ frame_needed = 1, uses_anonymous_args = 0
+	@ link register save eliminated.
+	stmfd	sp!, {r4, fp}
+	add	fp, sp, #4
+	sub	sp, sp, #13312
+	sub	sp, sp, #56
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r0, [ip, r3]
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	str	r1, [r0, r3]
+	movw	r3, #52172
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, .L2
+	vldr	d17, .L2+8
+	vstmia	r3, {d16-d17}
+	movw	r3, #53152
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #21844
+	movt	r3, 5461
+	vdup.32	q8, r3
+	vstmia	r2, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #12
+	vldmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #40
+	vldmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L2+16
+	vldr	d19, .L2+24
+	vstr	d18, [fp, #-20]
+	vstr	d19, [fp, #-12]
+	movw	r3, #63456
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63440
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-20]
+	vldr	d17, [fp, #-12]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63456
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L2+32
+	vldr	d21, .L2+40
+	vstr	d20, [fp, #-36]
+	vstr	d21, [fp, #-28]
+	movw	r3, #63424
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63408
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-36]
+	vldr	d17, [fp, #-28]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63424
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63408
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #63392
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63392
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63376
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L2+48
+	vldr	d19, .L2+56
+	vstr	d18, [fp, #-52]
+	vstr	d19, [fp, #-44]
+	movw	r3, #63360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63344
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-52]
+	vldr	d17, [fp, #-44]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63360
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L2+64
+	vldr	d21, .L2+72
+	vstr	d20, [fp, #-68]
+	vstr	d21, [fp, #-60]
+	movw	r3, #63328
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63312
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-68]
+	vldr	d17, [fp, #-60]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63328
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63312
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #63296
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63296
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63280
+	movt	r3, 65535
+	sub	r2, fp, #4
+	b	.L3
+.L4:
+	.align	3
+.L2:
+	.word	1431655760
+	.word	1521134245
+	.word	1610612730
+	.word	1700091215
+	.word	1
+	.word	2
+	.word	3
+	.word	4
+	.word	-31
+	.word	-30
+	.word	-29
+	.word	-28
+	.word	4
+	.word	5
+	.word	6
+	.word	7
+	.word	-28
+	.word	-27
+	.word	-26
+	.word	-25
+	.word	11
+	.word	12
+	.word	13
+	.word	14
+	.word	-21
+	.word	-20
+	.word	-19
+	.word	-18
+.L3:
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L2+80
+	vldr	d19, .L2+88
+	vstr	d18, [fp, #-84]
+	vstr	d19, [fp, #-76]
+	movw	r3, #63264
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63248
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-84]
+	vldr	d17, [fp, #-76]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63264
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63248
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L2+96
+	vldr	d21, .L2+104
+	vstr	d20, [fp, #-100]
+	vstr	d21, [fp, #-92]
+	mov	r3, #63232
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-100]
+	vldr	d17, [fp, #-92]
+	vstmia	r3, {d16-d17}
+	mov	r3, #63232
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #63200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63184
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63168
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63152
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63136
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #63120
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63120
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vsub.i32	q8, q8, q10
+	movw	r3, #63104
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63088
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63104
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63088
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #52172
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #28
+	vldmia	r3, {d16-d17}
+	movw	r3, #63072
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63072
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63056
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63040
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63024
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63040
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63024
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #16
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #28
+	vldmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #56
+	vldmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L5
+	vldr	d19, .L5+8
+	vstr	d18, [fp, #-116]
+	vstr	d19, [fp, #-108]
+	movw	r3, #63008
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62992
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-116]
+	vldr	d17, [fp, #-108]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63008
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L5+16
+	vldr	d21, .L5+24
+	vstr	d20, [fp, #-132]
+	vstr	d21, [fp, #-124]
+	mov	r3, #62976
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-132]
+	vldr	d17, [fp, #-124]
+	vstmia	r3, {d16-d17}
+	mov	r3, #62976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62960
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62944
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62928
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L5+32
+	vldr	d19, .L5+40
+	vstr	d18, [fp, #-148]
+	vstr	d19, [fp, #-140]
+	movw	r3, #62912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62896
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-148]
+	vldr	d17, [fp, #-140]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62912
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L5+48
+	vldr	d21, .L5+56
+	vstr	d20, [fp, #-164]
+	vstr	d21, [fp, #-156]
+	movw	r3, #62880
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62864
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-164]
+	vldr	d17, [fp, #-156]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62880
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62864
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62848
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62832
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62848
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62832
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L5+64
+	vldr	d19, .L5+72
+	vstr	d18, [fp, #-180]
+	vstr	d19, [fp, #-172]
+	movw	r3, #62816
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-180]
+	vldr	d17, [fp, #-172]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62816
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62800
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	b	.L6
+.L7:
+	.align	3
+.L5:
+	.word	5
+	.word	6
+	.word	7
+	.word	8
+	.word	-27
+	.word	-26
+	.word	-25
+	.word	-24
+	.word	8
+	.word	9
+	.word	10
+	.word	11
+	.word	-24
+	.word	-23
+	.word	-22
+	.word	-21
+	.word	15
+	.word	16
+	.word	1
+	.word	2
+	.word	-17
+	.word	-16
+	.word	-31
+	.word	-30
+.L6:
+	vldr	d20, .L5+80
+	vldr	d21, .L5+88
+	vstr	d20, [fp, #-196]
+	vstr	d21, [fp, #-188]
+	movw	r3, #62784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62768
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-196]
+	vldr	d17, [fp, #-188]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62784
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62736
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62752
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #62720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #62720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62704
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62688
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62672
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62672
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vsub.i32	q8, q8, q10
+	movw	r3, #62656
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62640
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62640
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #52172
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #44
+	vldmia	r3, {d16-d17}
+	movw	r3, #62624
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62608
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62608
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53264
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62592
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62576
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62592
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62576
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #32
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #44
+	vldmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #72
+	vldmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L8
+	vldr	d19, .L8+8
+	vstr	d18, [fp, #-212]
+	vstr	d19, [fp, #-204]
+	movw	r3, #62560
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62544
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-212]
+	vldr	d17, [fp, #-204]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62560
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62544
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L8+16
+	vldr	d21, .L8+24
+	vstr	d20, [fp, #-228]
+	vstr	d21, [fp, #-220]
+	movw	r3, #62528
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62512
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-228]
+	vldr	d17, [fp, #-220]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62528
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62512
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62496
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62480
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62496
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62480
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L8+32
+	vldr	d19, .L8+40
+	vstr	d18, [fp, #-244]
+	vstr	d19, [fp, #-236]
+	mov	r3, #62464
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62448
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-244]
+	vldr	d17, [fp, #-236]
+	vstmia	r3, {d16-d17}
+	mov	r3, #62464
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62448
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L8+48
+	vldr	d21, .L8+56
+	vstr	d20, [fp, #-260]
+	vstr	d21, [fp, #-252]
+	movw	r3, #62432
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62416
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-260]
+	vldr	d17, [fp, #-252]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62432
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62416
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62400
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62384
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62384
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L8+64
+	vldr	d19, .L8+72
+	vstr	d18, [fp, #-276]
+	vstr	d19, [fp, #-268]
+	movw	r3, #62368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62352
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-276]
+	vldr	d17, [fp, #-268]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62368
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62352
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	b	.L9
+.L10:
+	.align	3
+.L8:
+	.word	9
+	.word	10
+	.word	11
+	.word	12
+	.word	-23
+	.word	-22
+	.word	-21
+	.word	-20
+	.word	12
+	.word	13
+	.word	14
+	.word	15
+	.word	-20
+	.word	-19
+	.word	-18
+	.word	-17
+	.word	3
+	.word	4
+	.word	5
+	.word	6
+	.word	-29
+	.word	-28
+	.word	-27
+	.word	-26
+.L9:
+	vldr	d20, .L8+80
+	vldr	d21, .L8+88
+	vstr	d20, [fp, #-292]
+	vstr	d21, [fp, #-284]
+	movw	r3, #62336
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62320
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-292]
+	vldr	d17, [fp, #-284]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62336
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62320
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62288
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62304
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62288
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62256
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62272
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62256
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62240
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62224
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62240
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62224
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vsub.i32	q8, q8, q10
+	mov	r3, #62208
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62192
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #62208
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #52172
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #60
+	vldmia	r3, {d16-d17}
+	movw	r3, #62176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62160
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	mov	r3, #53248
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62128
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62128
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #48
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #60
+	vldmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #88
+	vldmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L11
+	vldr	d19, .L11+8
+	vstr	d18, [fp, #-308]
+	vstr	d19, [fp, #-300]
+	movw	r3, #62112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-308]
+	vldr	d17, [fp, #-300]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62112
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62096
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L11+16
+	vldr	d21, .L11+24
+	vstr	d20, [fp, #-324]
+	vstr	d21, [fp, #-316]
+	movw	r3, #62080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-324]
+	vldr	d17, [fp, #-316]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62064
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62048
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62032
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62048
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62032
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L11+32
+	vldr	d19, .L11+40
+	vstr	d18, [fp, #-340]
+	vstr	d19, [fp, #-332]
+	movw	r3, #62016
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62000
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-340]
+	vldr	d17, [fp, #-332]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62016
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62000
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L11+48
+	vldr	d21, .L11+56
+	vstr	d20, [fp, #-356]
+	vstr	d21, [fp, #-348]
+	movw	r3, #61984
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61968
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-356]
+	vldr	d17, [fp, #-348]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61984
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61968
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	mov	r3, #61952
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61936
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #61952
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61936
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L11+64
+	vldr	d19, .L11+72
+	vstr	d18, [fp, #-372]
+	vstr	d19, [fp, #-364]
+	movw	r3, #61920
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61904
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-372]
+	vldr	d17, [fp, #-364]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61920
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61904
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	b	.L12
+.L13:
+	.align	3
+.L11:
+	.word	13
+	.word	14
+	.word	15
+	.word	16
+	.word	-19
+	.word	-18
+	.word	-17
+	.word	-16
+	.word	16
+	.word	1
+	.word	2
+	.word	3
+	.word	-16
+	.word	-31
+	.word	-30
+	.word	-29
+	.word	7
+	.word	8
+	.word	9
+	.word	10
+	.word	-25
+	.word	-24
+	.word	-23
+	.word	-22
+.L12:
+	vldr	d20, .L11+80
+	vldr	d21, .L11+88
+	vstr	d20, [fp, #-388]
+	vstr	d21, [fp, #-380]
+	movw	r3, #61888
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61872
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-388]
+	vldr	d17, [fp, #-380]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61888
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #61856
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61840
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61856
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61840
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61808
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61824
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61808
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61792
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #61776
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61792
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61776
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vsub.i32	q8, q8, q10
+	movw	r3, #61760
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61744
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61760
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61744
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #52172
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #12
+	vldmia	r3, {d16-d17}
+	movw	r3, #61728
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61712
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61728
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61712
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53232
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #61696
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61680
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #61696
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61680
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53168
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L14
+	vldr	d19, .L14+8
+	vstr	d18, [fp, #-404]
+	vstr	d19, [fp, #-396]
+	movw	r3, #61664
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61648
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-404]
+	vldr	d17, [fp, #-396]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61664
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61648
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L14+80
+	vldr	d21, .L14+88
+	vstr	d20, [fp, #-420]
+	vstr	d21, [fp, #-412]
+	movw	r3, #61632
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61616
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-420]
+	vldr	d17, [fp, #-412]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61632
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61616
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #61600
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61584
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61600
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61584
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L14+96
+	vldr	d21, .L14+104
+	vstr	d20, [fp, #-436]
+	vstr	d21, [fp, #-428]
+	movw	r3, #61568
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61552
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-436]
+	vldr	d17, [fp, #-428]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61568
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61552
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L14+16
+	vldr	d23, .L14+24
+	vstr	d22, [fp, #-452]
+	vstr	d23, [fp, #-444]
+	movw	r3, #61536
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61520
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-452]
+	vldr	d17, [fp, #-444]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61536
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61520
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #61504
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #61488
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #61488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L14+32
+	vldr	d23, .L14+40
+	vstr	d22, [fp, #-468]
+	vstr	d23, [fp, #-460]
+	movw	r3, #61472
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61456
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-468]
+	vldr	d17, [fp, #-460]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61456
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L14+48
+	vldr	d25, .L14+56
+	vstr	d24, [fp, #-484]
+	vstr	d25, [fp, #-476]
+	mov	r3, #61440
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61424
+	movt	r3, 65535
+	sub	r1, fp, #4
+	b	.L15
+.L16:
+	.align	3
+.L14:
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	23
+	.word	25
+	.word	29
+	.word	19
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	3
+	.word	8
+	.word	12
+	.word	15
+	.word	4
+.L15:
+	add	r3, r1, r3
+	vldr	d16, [fp, #-484]
+	vldr	d17, [fp, #-476]
+	vstmia	r3, {d16-d17}
+	mov	r3, #61440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61424
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #61408
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #61392
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61408
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #61392
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #61376
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #61360
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61376
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #61360
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #61344
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61328
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61344
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61328
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #16
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L14+64
+	vldr	d19, .L14+72
+	vstr	d18, [fp, #-500]
+	vstr	d19, [fp, #-492]
+	movw	r3, #61312
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61296
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-500]
+	vldr	d17, [fp, #-492]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61312
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61296
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L14+80
+	vldr	d21, .L14+88
+	vstr	d20, [fp, #-516]
+	vstr	d21, [fp, #-508]
+	movw	r3, #61280
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61264
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-516]
+	vldr	d17, [fp, #-508]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61280
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61264
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #61248
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61232
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61248
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61232
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L14+96
+	vldr	d21, .L14+104
+	vstr	d20, [fp, #-532]
+	vstr	d21, [fp, #-524]
+	movw	r3, #61216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-532]
+	vldr	d17, [fp, #-524]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L17
+	vldr	d23, .L17+8
+	vstr	d22, [fp, #-548]
+	vstr	d23, [fp, #-540]
+	mov	r3, #61184
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61168
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-548]
+	vldr	d17, [fp, #-540]
+	vstmia	r3, {d16-d17}
+	mov	r3, #61184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61168
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #61152
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #61136
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61152
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #61136
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L17+96
+	vldr	d23, .L17+104
+	vstr	d22, [fp, #-564]
+	vstr	d23, [fp, #-556]
+	movw	r3, #61120
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61104
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-564]
+	vldr	d17, [fp, #-556]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61120
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61104
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L17+16
+	vldr	d25, .L17+24
+	vstr	d24, [fp, #-580]
+	vstr	d25, [fp, #-572]
+	movw	r3, #61088
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61072
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-580]
+	vldr	d17, [fp, #-572]
+	vstmia	r3, {d16-d17}
+	movw	r3, #61088
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61072
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #61056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #61040
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61056
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #61040
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #61024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #61008
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61024
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #61008
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #60992
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60992
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #60976
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60960
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60960
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60944
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	b	.L18
+.L19:
+	.align	3
+.L17:
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	3
+	.word	8
+	.word	12
+	.word	15
+	.word	4
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	23
+	.word	25
+	.word	29
+	.word	19
+.L18:
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #32
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L17+32
+	vldr	d19, .L17+40
+	vstr	d18, [fp, #-596]
+	vstr	d19, [fp, #-588]
+	mov	r3, #60928
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60912
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-596]
+	vldr	d17, [fp, #-588]
+	vstmia	r3, {d16-d17}
+	mov	r3, #60928
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60912
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L17+48
+	vldr	d21, .L17+56
+	vstr	d20, [fp, #-612]
+	vstr	d21, [fp, #-604]
+	movw	r3, #60896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60880
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-612]
+	vldr	d17, [fp, #-604]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60896
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60880
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #60864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60864
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #60848
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L17+64
+	vldr	d21, .L17+72
+	vstr	d20, [fp, #-628]
+	vstr	d21, [fp, #-620]
+	movw	r3, #60832
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60816
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-628]
+	vldr	d17, [fp, #-620]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60832
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60816
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L17+80
+	vldr	d23, .L17+88
+	vstr	d22, [fp, #-644]
+	vstr	d23, [fp, #-636]
+	movw	r3, #60800
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60784
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-644]
+	vldr	d17, [fp, #-636]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #60768
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #60752
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #60752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L17+96
+	vldr	d23, .L17+104
+	vstr	d22, [fp, #-660]
+	vstr	d23, [fp, #-652]
+	movw	r3, #60736
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-660]
+	vldr	d17, [fp, #-652]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L20
+	vldr	d25, .L20+8
+	vstr	d24, [fp, #-676]
+	vstr	d25, [fp, #-668]
+	movw	r3, #60704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-676]
+	vldr	d17, [fp, #-668]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60704
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60688
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	mov	r3, #60672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #60656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #60672
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #60656
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #60640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #60624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60640
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #60624
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #60608
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60592
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60608
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #60592
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60576
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60560
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60576
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60560
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #48
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L20+16
+	vldr	d19, .L20+24
+	vstr	d18, [fp, #-692]
+	vstr	d19, [fp, #-684]
+	movw	r3, #60544
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60528
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-692]
+	vldr	d17, [fp, #-684]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60544
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60528
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L20+32
+	vldr	d21, .L20+40
+	vstr	d20, [fp, #-708]
+	vstr	d21, [fp, #-700]
+	movw	r3, #60512
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60496
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-708]
+	vldr	d17, [fp, #-700]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60512
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60496
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #60480
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60464
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	b	.L21
+.L22:
+	.align	3
+.L20:
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	3
+	.word	8
+	.word	12
+	.word	15
+	.word	4
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	23
+	.word	25
+	.word	29
+	.word	19
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+.L21:
+	vstmia	r3, {d16-d17}
+	movw	r3, #60480
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #60464
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L20+48
+	vldr	d21, .L20+56
+	vstr	d20, [fp, #-724]
+	vstr	d21, [fp, #-716]
+	movw	r3, #60448
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60432
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-724]
+	vldr	d17, [fp, #-716]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60448
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60432
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L20+64
+	vldr	d23, .L20+72
+	vstr	d22, [fp, #-740]
+	vstr	d23, [fp, #-732]
+	mov	r3, #60416
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60400
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-740]
+	vldr	d17, [fp, #-732]
+	vstmia	r3, {d16-d17}
+	mov	r3, #60416
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60400
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #60384
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #60368
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60384
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #60368
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L20+80
+	vldr	d23, .L20+88
+	vstr	d22, [fp, #-756]
+	vstr	d23, [fp, #-748]
+	movw	r3, #60352
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60336
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-756]
+	vldr	d17, [fp, #-748]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60352
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60336
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L20+96
+	vldr	d25, .L20+104
+	vstr	d24, [fp, #-772]
+	vstr	d25, [fp, #-764]
+	movw	r3, #60320
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-772]
+	vldr	d17, [fp, #-764]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60320
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60304
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #60288
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #60272
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60288
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #60272
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #60256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #60240
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60256
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #60240
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #60224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60208
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60224
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #60208
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60192
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60176
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #60160
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #60160
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60136
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #60128
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #60136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #60128
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #64
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #60120
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #60120
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r1, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #60112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #60112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r1, r1, r3
+	movw	r3, #53280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60096
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vmov.32	r3, d16[0]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #4
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L23
+	vldr	d19, .L23+8
+	vstr	d18, [fp, #-788]
+	vstr	d19, [fp, #-780]
+	movw	r3, #60080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-788]
+	vldr	d17, [fp, #-780]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60064
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L23+80
+	vldr	d21, .L23+88
+	vstr	d20, [fp, #-804]
+	vstr	d21, [fp, #-796]
+	movw	r3, #60048
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60032
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-804]
+	vldr	d17, [fp, #-796]
+	vstmia	r3, {d16-d17}
+	movw	r3, #60048
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #60032
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #60016
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #60000
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #60016
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #60000
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L23+96
+	vldr	d21, .L23+104
+	vstr	d20, [fp, #-820]
+	vstr	d21, [fp, #-812]
+	movw	r3, #59984
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59968
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-820]
+	vldr	d17, [fp, #-812]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59984
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59968
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L23+16
+	vldr	d23, .L23+24
+	vstr	d22, [fp, #-836]
+	vstr	d23, [fp, #-828]
+	movw	r3, #59952
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59936
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-836]
+	vldr	d17, [fp, #-828]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59952
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59936
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #59920
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	mov	r3, #59904
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59920
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	mov	r3, #59904
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L23+32
+	vldr	d23, .L23+40
+	vstr	d22, [fp, #-852]
+	vstr	d23, [fp, #-844]
+	movw	r3, #59888
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-852]
+	vldr	d17, [fp, #-844]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59888
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59872
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L23+48
+	vldr	d25, .L23+56
+	vstr	d24, [fp, #-868]
+	vstr	d25, [fp, #-860]
+	movw	r3, #59856
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59840
+	movt	r3, 65535
+	sub	r2, fp, #4
+	b	.L24
+.L25:
+	.align	3
+.L23:
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	23
+	.word	25
+	.word	29
+	.word	19
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	3
+	.word	8
+	.word	12
+	.word	15
+	.word	4
+.L24:
+	add	r3, r2, r3
+	vldr	d16, [fp, #-868]
+	vldr	d17, [fp, #-860]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59856
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59840
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #59824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #59808
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59824
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #59808
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #59792
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #59776
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59792
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #59776
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #59760
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #59744
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59760
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #59744
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #20
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L23+64
+	vldr	d19, .L23+72
+	vstr	d18, [fp, #-884]
+	vstr	d19, [fp, #-876]
+	movw	r3, #59728
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59712
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-884]
+	vldr	d17, [fp, #-876]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59728
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59712
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L23+80
+	vldr	d21, .L23+88
+	vstr	d20, [fp, #-900]
+	vstr	d21, [fp, #-892]
+	movw	r3, #59696
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59680
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-900]
+	vldr	d17, [fp, #-892]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59696
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59680
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #59664
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #59648
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59664
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	mov	r3, #59648
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L23+96
+	vldr	d21, .L23+104
+	vstr	d20, [fp, #-916]
+	vstr	d21, [fp, #-908]
+	movw	r3, #59632
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59616
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-916]
+	vldr	d17, [fp, #-908]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59632
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59616
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L26
+	vldr	d23, .L26+8
+	vstr	d22, [fp, #-932]
+	vstr	d23, [fp, #-924]
+	movw	r3, #59600
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59584
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-932]
+	vldr	d17, [fp, #-924]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59600
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59584
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #59568
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #59552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59568
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #59552
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L26+96
+	vldr	d23, .L26+104
+	vstr	d22, [fp, #-948]
+	vstr	d23, [fp, #-940]
+	movw	r3, #59536
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59520
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-948]
+	vldr	d17, [fp, #-940]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59536
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59520
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L26+16
+	vldr	d25, .L26+24
+	vstr	d24, [fp, #-964]
+	vstr	d25, [fp, #-956]
+	movw	r3, #59504
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59488
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-964]
+	vldr	d17, [fp, #-956]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #59472
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #59456
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59472
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #59456
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #59440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #59424
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59440
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #59424
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #59408
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #59392
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59408
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	mov	r3, #59392
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #59360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59376
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59360
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	b	.L27
+.L28:
+	.align	3
+.L26:
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	3
+	.word	8
+	.word	12
+	.word	15
+	.word	4
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	23
+	.word	25
+	.word	29
+	.word	19
+.L27:
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #36
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L26+32
+	vldr	d19, .L26+40
+	vstr	d18, [fp, #-980]
+	vstr	d19, [fp, #-972]
+	movw	r3, #59344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-980]
+	vldr	d17, [fp, #-972]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59344
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59328
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L26+48
+	vldr	d21, .L26+56
+	vstr	d20, [fp, #-996]
+	vstr	d21, [fp, #-988]
+	movw	r3, #59312
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59296
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldr	d16, [fp, #-996]
+	vldr	d17, [fp, #-988]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59312
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59296
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #59280
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #59264
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #59264
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L26+64
+	vldr	d21, .L26+72
+	vstr	d20, [fp, #-1012]
+	vstr	d21, [fp, #-1004]
+	movw	r3, #59248
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59232
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d16, [fp, #-1012]
+	vldr	d17, [fp, #-1004]
+	vstmia	r3, {d16-d17}
+	movw	r3, #59248
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59232
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #64512
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d22, .L26+80
+	vldr	d23, .L26+88
+	vstmia	r3, {d22-d23}
+	movw	r3, #59216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	mov	r3, #64512
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #59216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #59184
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #59168
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #59168
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64496
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d22, .L26+96
+	vldr	d23, .L26+104
+	vstmia	r3, {d22-d23}
+	movw	r3, #59152
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #59136
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64496
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #59152
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #59136
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64480
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d24, .L29
+	vldr	d25, .L29+8
+	vstmia	r3, {d24-d25}
+	movw	r3, #59120
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59104
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64480
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #59120
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #59104
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #59088
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #59072
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59088
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #59072
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #59056
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #59040
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #59040
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #59024
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #59008
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #59024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #59008
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58976
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58992
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58976
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #52
+	vldmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64464
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d18, .L29+16
+	vldr	d19, .L29+24
+	vstmia	r3, {d18-d19}
+	movw	r3, #58960
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58944
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r2, r0, r3
+	movw	r3, #64464
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58960
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58944
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64448
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d20, .L29+32
+	vldr	d21, .L29+40
+	vstmia	r3, {d20-d21}
+	movw	r3, #58928
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58912
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64448
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	b	.L30
+.L31:
+	.align	3
+.L29:
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	3
+	.word	8
+	.word	12
+	.word	15
+	.word	4
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	-28
+	.word	23
+	.word	25
+	.word	29
+	.word	19
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-13
+.L30:
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #58896
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #58880
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	mov	r3, #58880
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64432
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L29+48
+	vldr	d21, .L29+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #58864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58848
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64432
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64416
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d22, .L29+64
+	vldr	d23, .L29+72
+	vstmia	r3, {d22-d23}
+	movw	r3, #58832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58816
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64416
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58816
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #58800
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #58784
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #58784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64400
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d22, .L29+80
+	vldr	d23, .L29+88
+	vstmia	r3, {d22-d23}
+	movw	r3, #58768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58752
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64400
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64384
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d24, .L29+96
+	vldr	d25, .L29+104
+	vstmia	r3, {d24-d25}
+	movw	r3, #58736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64384
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #58704
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #58688
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #58688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #58672
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #58656
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #58656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #58640
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #58624
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	mov	r3, #58624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58608
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58592
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58608
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58592
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58576
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58576
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58560
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58560
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #58544
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58552
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58544
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #68
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58536
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58536
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r1, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58528
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58528
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r1, r1, r3
+	movw	r3, #53280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58512
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58512
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vmov.32	r3, d16[1]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r2, r3, #8
+	movw	r3, #58508
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #58508
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #53048
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53048
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #40
+	movw	r3, #58504
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #58504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #53016
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53016
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #53080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58500
+	movt	r3, 65535
+	mov	r2, #0
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #58480
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58500
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r2, [r1, r3]
+	movw	r3, #58480
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vmov.32	d17[1], r2
+	movw	r3, #53080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58464
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58448
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58464
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58448
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58432
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58432
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58416
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58416
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58408
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #58400
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58408
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58392
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58392
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r2, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58384
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58384
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #72
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #64
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #64
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d18, .L32
+	vldr	d19, .L32+8
+	vstmia	r3, {d18-d19}
+	mov	r3, #58368
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58352
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r2, r0, r3
+	movw	r3, #64360
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	mov	r3, #58368
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58352
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d20, .L32+16
+	vldr	d21, .L32+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #58336
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58320
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64344
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58336
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58320
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #58304
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58288
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58304
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #58288
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64328
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L32+32
+	vldr	d19, .L32+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #58272
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58256
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64328
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58256
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64312
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L32+48
+	vldr	d21, .L32+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #58240
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58224
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64312
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #58240
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58224
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #58208
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58192
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58208
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #58192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58176
+	b	.L33
+.L34:
+	.align	3
+.L32:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L33:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58160
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58128
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58128
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58120
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	mov	r3, #58112
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58120
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	mov	r3, #58112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #72
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #72
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58104
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58104
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #58096
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #58096
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #12
+	movw	r3, #58092
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #58092
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52984
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53296
+	movt	r2, 65535
+	movw	r3, #52984
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53296
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #44
+	movw	r3, #58088
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #58088
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52952
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53328
+	movt	r2, 65535
+	movw	r3, #52952
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53328
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #53080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58084
+	movt	r3, 65535
+	mov	r2, #0
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #58064
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58084
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r2, [r1, r3]
+	movw	r3, #58064
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	vmov.32	d17[1], r2
+	movw	r3, #53080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58048
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #58032
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58048
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58032
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58016
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58016
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #58000
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #58000
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #57984
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57992
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57984
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57976
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57976
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r2, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57968
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57968
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #76
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #68
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r3, r3, #68
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64288
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d18, .L35
+	vldr	d19, .L35+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #57952
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57936
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r2, r0, r3
+	movw	r3, #64288
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57952
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57936
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d20, .L35+16
+	vldr	d21, .L35+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #57920
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57904
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64272
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57920
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57904
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57888
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57872
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57888
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #57872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	mov	r3, #64256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L35+32
+	vldr	d19, .L35+40
+	vstmia	r3, {d18-d19}
+	mov	r3, #57856
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57840
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	mov	r3, #64256
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	mov	r3, #57856
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57840
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64240
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L35+48
+	vldr	d21, .L35+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #57824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57808
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64240
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57808
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57792
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57776
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57792
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #57776
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57760
+	b	.L36
+.L37:
+	.align	3
+.L35:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L36:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57744
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57760
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57744
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57728
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57728
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57712
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57712
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #57696
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57704
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57696
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #76
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #76
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57688
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57688
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57680
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57680
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #16
+	movw	r3, #57676
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #57676
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52920
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53360
+	movt	r2, 65535
+	movw	r3, #52920
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53360
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #48
+	movw	r3, #57672
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #57672
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52888
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53392
+	movt	r2, 65535
+	movw	r3, #52888
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53392
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #64
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #8
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1160]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #80
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #72
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #72
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L38
+	vldr	d19, .L38+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #57656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57640
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64224
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57640
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64208
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L38+16
+	vldr	d21, .L38+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #57624
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57608
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64208
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57624
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57608
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57592
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57576
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57592
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #57576
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64192
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L38+32
+	vldr	d19, .L38+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #57560
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57544
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64192
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57560
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57544
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L38+48
+	vldr	d21, .L38+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #57528
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57512
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57528
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57512
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57496
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57480
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57496
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #57480
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57464
+	b	.L39
+.L40:
+	.align	3
+.L38:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L39:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57448
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57464
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57448
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57432
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57432
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57416
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57416
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57408
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #57400
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57408
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57400
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #80
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #80
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57392
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57392
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57384
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57384
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #20
+	movw	r3, #57380
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #57380
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52856
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53424
+	movt	r2, 65535
+	movw	r3, #52856
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53424
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #52
+	movw	r3, #57376
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #57376
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53456
+	movt	r2, 65535
+	movw	r3, #52824
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53456
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #68
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #12
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1232]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #84
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #76
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #76
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L41
+	vldr	d19, .L41+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #57360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #57344
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64160
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57360
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #57344
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L41+16
+	vldr	d21, .L41+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #57328
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57312
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57328
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57312
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57296
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57296
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #57280
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64128
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L41+32
+	vldr	d19, .L41+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #57264
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57248
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64128
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57264
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57248
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L41+48
+	vldr	d21, .L41+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #57232
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57232
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #57184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57168
+	b	.L42
+.L43:
+	.align	3
+.L41:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L42:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #57152
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57168
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57152
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57136
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57120
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57120
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57112
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #57104
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57104
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #84
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #84
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #57096
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #57096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	mov	r3, #57088
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	mov	r3, #57088
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #24
+	movw	r3, #57084
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #57084
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52792
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53488
+	movt	r2, 65535
+	movw	r3, #52792
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53488
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #56
+	movw	r3, #57080
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #57080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52760
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53520
+	movt	r2, 65535
+	movw	r3, #52760
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53520
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #72
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #16
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1160]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #88
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #80
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #80
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64096
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L44
+	vldr	d19, .L44+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #57064
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57048
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57048
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L44+16
+	vldr	d21, .L44+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #57032
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57016
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64080
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #57032
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #57016
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #57000
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56984
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #57000
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56984
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L44+32
+	vldr	d19, .L44+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #56968
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56952
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64064
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56968
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56952
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64048
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L44+48
+	vldr	d21, .L44+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #56936
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56920
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64048
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56936
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56920
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56904
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56888
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56904
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56888
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56872
+	b	.L45
+.L46:
+	.align	3
+.L44:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L45:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56856
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56872
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56856
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56840
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56840
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56824
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56824
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56816
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #56808
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56816
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56808
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #88
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #88
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56800
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56800
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56792
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56792
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #28
+	movw	r3, #56788
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #56788
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52728
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53552
+	movt	r2, 65535
+	movw	r3, #52728
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53552
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #60
+	movw	r3, #56784
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #56784
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52696
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53584
+	movt	r2, 65535
+	movw	r3, #52696
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53584
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #76
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #20
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1232]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #92
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #84
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #84
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64032
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L47
+	vldr	d19, .L47+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #56768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56752
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64032
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #64016
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L47+16
+	vldr	d21, .L47+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #56736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #64016
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56704
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56688
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	mov	r3, #64000
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L47+32
+	vldr	d19, .L47+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #56672
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56656
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	mov	r3, #64000
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63984
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L47+48
+	vldr	d21, .L47+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #56640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56624
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63984
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56608
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56592
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56608
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56592
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #56576
+	b	.L48
+.L49:
+	.align	3
+.L47:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L48:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56560
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #56576
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56560
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56544
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56544
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56528
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56528
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56520
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #56512
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56520
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56512
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #92
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #92
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56504
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56496
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56496
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #32
+	movw	r3, #56492
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #56492
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52664
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53616
+	movt	r2, 65535
+	movw	r3, #52664
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53616
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #64
+	movw	r3, #56488
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #56488
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52632
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53648
+	movt	r2, 65535
+	movw	r3, #52632
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53648
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #80
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #24
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1160]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #96
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #88
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #88
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63968
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L50
+	vldr	d19, .L50+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #56472
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56456
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63968
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56456
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63952
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L50+16
+	vldr	d21, .L50+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #56440
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56424
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63952
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56440
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56424
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56408
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56392
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56408
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56392
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63936
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L50+32
+	vldr	d19, .L50+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #56376
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56360
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63936
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63920
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L50+48
+	vldr	d21, .L50+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #56344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56328
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63920
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56312
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56296
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56312
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56296
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56280
+	b	.L51
+.L52:
+	.align	3
+.L50:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L51:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56264
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56264
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56248
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56248
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56232
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56232
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #56216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56224
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #96
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #96
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56208
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56208
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #56200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #56200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #36
+	movw	r3, #56196
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #56196
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52600
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53680
+	movt	r2, 65535
+	movw	r3, #52600
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53680
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #68
+	movw	r3, #56192
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #56192
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52568
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53712
+	movt	r2, 65535
+	movw	r3, #52568
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53712
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #84
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #28
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1232]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #100
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #92
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #92
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63904
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L53
+	vldr	d19, .L53+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #56176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56160
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63904
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56160
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63888
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L53+16
+	vldr	d21, .L53+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #56144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56128
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63888
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56128
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56112
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56112
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56096
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L53+32
+	vldr	d19, .L53+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #56080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #56064
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56080
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #56064
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63856
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L53+48
+	vldr	d21, .L53+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #56048
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56032
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63856
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #56048
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #56032
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #56016
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #56000
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #56016
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #56000
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55984
+	b	.L54
+.L55:
+	.align	3
+.L53:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L54:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55968
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55984
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55968
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55952
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55952
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55936
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55936
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #55920
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55928
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55920
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #100
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #100
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55912
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55912
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55904
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55904
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #40
+	movw	r3, #55900
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #55900
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52536
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53744
+	movt	r2, 65535
+	movw	r3, #52536
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53744
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #72
+	movw	r3, #55896
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #55896
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52504
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53776
+	movt	r2, 65535
+	movw	r3, #52504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53776
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #88
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #32
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1160]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #104
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #96
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #96
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63840
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L56
+	vldr	d19, .L56+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #55880
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55864
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63840
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55880
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55864
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63824
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L56+16
+	vldr	d21, .L56+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #55848
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55832
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63824
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55848
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55832
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #55816
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55800
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55816
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #55800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63808
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L56+32
+	vldr	d19, .L56+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #55784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55768
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63808
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63792
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L56+48
+	vldr	d21, .L56+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #55752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55736
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63792
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #55720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55704
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #55704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55688
+	b	.L57
+.L58:
+	.align	3
+.L56:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L57:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55672
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55688
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55656
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55640
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55640
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55632
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #55624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55632
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55624
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #104
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #104
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55616
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55616
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55608
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55608
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #44
+	movw	r3, #55604
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #55604
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52472
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53808
+	movt	r2, 65535
+	movw	r3, #52472
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53808
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #76
+	movw	r3, #55600
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #55600
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52440
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53840
+	movt	r2, 65535
+	movw	r3, #52440
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53840
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #92
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #36
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1232]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #108
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #100
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #100
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63776
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L59
+	vldr	d19, .L59+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #55584
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55568
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63776
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55584
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55568
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63760
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L59+16
+	vldr	d21, .L59+24
+	vstmia	r3, {d20-d21}
+	mov	r3, #55552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55536
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63760
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	mov	r3, #55552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55536
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #55520
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55520
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #55504
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	mov	r3, #63744
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L59+32
+	vldr	d19, .L59+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #55488
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55472
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	mov	r3, #63744
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55472
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63728
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L59+48
+	vldr	d21, .L59+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #55456
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55440
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63728
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55456
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #55424
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55408
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55424
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #55408
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55392
+	b	.L60
+.L61:
+	.align	3
+.L59:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L60:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55376
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55392
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55360
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55360
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55344
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55344
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55336
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #55328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55336
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55328
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #108
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #108
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55320
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55320
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55312
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55312
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #48
+	movw	r3, #55308
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #55308
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52408
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53872
+	movt	r2, 65535
+	movw	r3, #52408
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53872
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #80
+	movw	r3, #55304
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #55304
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53904
+	movt	r2, 65535
+	movw	r3, #52376
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53904
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #96
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #40
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1160]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #112
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #104
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #104
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63712
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L62
+	vldr	d19, .L62+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #55288
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55272
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63712
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55288
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55272
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63696
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L62+16
+	vldr	d21, .L62+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #55256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55240
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63696
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55240
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #55224
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55208
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #55208
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63680
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L62+32
+	vldr	d19, .L62+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #55192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55176
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63680
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55192
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55176
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63664
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L62+48
+	vldr	d21, .L62+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #55160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63664
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #55160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #55128
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55112
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55128
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #55112
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55096
+	b	.L63
+.L64:
+	.align	3
+.L62:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L63:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #55080
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55080
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55064
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #55048
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #55048
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #55040
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #55032
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	mov	r3, #55040
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55032
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #112
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #112
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55024
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55024
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #55016
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #55016
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #52
+	movw	r3, #55012
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #55012
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52344
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53936
+	movt	r2, 65535
+	movw	r3, #52344
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #53936
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #84
+	movw	r3, #55008
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #55008
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52312
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #53968
+	movt	r2, 65535
+	movw	r3, #52312
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #53968
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #100
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #44
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1232]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #116
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #108
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #108
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63648
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L65
+	vldr	d19, .L65+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #54992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54976
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63648
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54992
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63632
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L65+16
+	vldr	d21, .L65+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #54960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54944
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63632
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #54928
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54912
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #54912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63616
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L65+32
+	vldr	d19, .L65+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #54896
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54880
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63616
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54880
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63600
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L65+48
+	vldr	d21, .L65+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #54864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54848
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63600
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #54832
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54816
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #54816
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54800
+	b	.L66
+.L67:
+	.align	3
+.L65:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L66:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #54784
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54800
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #54784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54768
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54752
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54752
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54744
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #54736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54744
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54736
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #116
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #116
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54728
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54728
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54720
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #56
+	movw	r3, #54716
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #54716
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52280
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #54000
+	movt	r2, 65535
+	movw	r3, #52280
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #54000
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #88
+	movw	r3, #54712
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #54712
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52248
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #54032
+	movt	r2, 65535
+	movw	r3, #52248
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #54032
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #104
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #48
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1160]
+	add	r3, r2, r3
+	str	r3, [fp, #-1160]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #120
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #112
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #112
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1160]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63584
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L68
+	vldr	d19, .L68+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #54696
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54680
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63584
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54696
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54680
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63568
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L68+16
+	vldr	d21, .L68+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #54664
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54648
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63568
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54664
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54648
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #54632
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54616
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54632
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #54616
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L68+32
+	vldr	d19, .L68+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #54600
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54584
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63552
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54600
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54584
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63536
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L68+48
+	vldr	d21, .L68+56
+	vstmia	r3, {d20-d21}
+	movw	r3, #54568
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54552
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63536
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54568
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54552
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #54536
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54520
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54536
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #54520
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54504
+	b	.L69
+.L70:
+	.align	3
+.L68:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L69:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54488
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54472
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54456
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54456
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54448
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #54440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54448
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54440
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #120
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #120
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54432
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54432
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54424
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54424
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #60
+	movw	r3, #54420
+	movt	r3, 65535
+	sub	r1, fp, #4
+	str	r2, [r1, r3]
+	movw	r3, #54420
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #54064
+	movt	r2, 65535
+	movw	r3, #52216
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53112
+	movt	r2, 65535
+	movw	r3, #54064
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #92
+	movw	r3, #54416
+	movt	r3, 65535
+	sub	ip, fp, #4
+	str	r2, [ip, r3]
+	movw	r3, #54416
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	vld2.32	{d16-d19}, [r3]
+	movw	r3, #52184
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d19}
+	movw	r2, #54096
+	movt	r2, 65535
+	movw	r3, #52184
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r2, #53080
+	movt	r2, 65535
+	movw	r3, #54096
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	ip, r0, r2
+	sub	r1, fp, #4
+	add	r4, r1, r3
+	ldmia	r4!, {r0, r1, r2, r3}
+	stmia	ip!, {r0, r1, r2, r3}
+	ldmia	r4, {r0, r1, r2, r3}
+	stmia	ip, {r0, r1, r2, r3}
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r3, r3, #108
+	ldr	r2, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #52
+	ldr	r3, [r3, #0]
+	rsb	r3, r3, r2
+	ldr	r2, [fp, #-1232]
+	add	r3, r2, r3
+	str	r3, [fp, #-1232]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r0, fp, #4
+	ldr	r3, [r0, r3]
+	add	r2, r3, #124
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r1, fp, #4
+	ldr	r3, [r1, r3]
+	add	r3, r3, #116
+	ldr	r3, [r3, #0]
+	mov	r1, r3, lsr #1
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #116
+	ldr	r3, [r3, #0]
+	orr	r1, r1, r3
+	ldr	r3, [fp, #-1232]
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63520
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L71
+	vldr	d19, .L71+8
+	vstmia	r3, {d18-d19}
+	movw	r3, #54400
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54384
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63520
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54384
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53112
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L71+16
+	vldr	d21, .L71+24
+	vstmia	r3, {d20-d21}
+	movw	r3, #54368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54352
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63504
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54352
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #54336
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54320
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54336
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #54320
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	mov	r3, #63488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d18, .L71+32
+	vldr	d19, .L71+40
+	vstmia	r3, {d18-d19}
+	movw	r3, #54304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54288
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	mov	r3, #63488
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	movw	r3, #54304
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54288
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #53080
+	movt	r3, 65535
+	mov	r2, #16
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	add	r3, r3, r2
+	vldmia	r3, {d16-d17}
+	movw	r3, #63472
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldr	d20, .L71+48
+	vldr	d21, .L71+56
+	vstmia	r3, {d20-d21}
+	mov	r3, #54272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54256
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r2, ip, r3
+	movw	r3, #63472
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	mov	r3, #54272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54256
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #54240
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54224
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54240
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #54224
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #53216
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54208
+	b	.L72
+.L73:
+	.align	3
+.L71:
+	.word	3
+	.word	7
+	.word	13
+	.word	16
+	.word	-29
+	.word	-25
+	.word	-19
+	.word	-16
+	.word	19
+	.word	23
+	.word	27
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-5
+	.word	-2
+.L72:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #54192
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54208
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54192
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54176
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov	d16, d17
+	vmov	d18, d16  @ v2si
+	movw	r3, #53200
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54160
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #54160
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #54152
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d18, [r3, #0]
+	movw	r3, #54144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54152
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d17, [r3, #0]
+	vadd.i32	d16, d16, d17
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	r2, fp, #4
+	ldr	r3, [r2, r3]
+	add	r2, r3, #124
+	movw	r3, #52180
+	movt	r3, 65535
+	sub	ip, fp, #4
+	ldr	r3, [ip, r3]
+	add	r3, r3, #124
+	ldr	r1, [r3, #0]
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54136
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54136
+	movt	r3, 65535
+	sub	r0, fp, #4
+	add	r3, r0, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[0]
+	mov	r0, r3
+	movw	r3, #53144
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	movw	r3, #54128
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #54128
+	movt	r3, 65535
+	sub	ip, fp, #4
+	add	r3, ip, r3
+	fldd	d16, [r3, #0]
+	vmov.32	r3, d16[1]
+	add	r3, r0, r3
+	add	r3, r1, r3
+	str	r3, [r2, #0]
+	sub	sp, fp, #4
+	ldmfd	sp!, {r4, fp}
+	bx	lr
+	.size	bmw_small_f1, .-bmw_small_f1
+	.align	2
+	.type	bmw_small_f0, %function
+bmw_small_f0:
+	@ args = 0, pretend = 0, frame = 3928
+	@ frame_needed = 1, uses_anonymous_args = 0
+	@ link register save eliminated.
+	str	fp, [sp, #-4]!
+	add	fp, sp, #0
+	sub	sp, sp, #3920
+	sub	sp, sp, #12
+	str	r0, [fp, #-3920]
+	str	r1, [fp, #-3924]
+	str	r2, [fp, #-3928]
+	ldr	r3, [fp, #-3924]
+	vldmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #16
+	vldmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #32
+	vldmia	r3, {d16-d17}
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #48
+	vldmia	r3, {d16-d17}
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3928]
+	vldmia	r3, {d16-d17}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3928]
+	add	r3, r3, #16
+	vldmia	r3, {d16-d17}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3928]
+	add	r3, r3, #32
+	vldmia	r3, {d16-d17}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3928]
+	add	r3, r3, #48
+	vldmia	r3, {d16-d17}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-756]
+	vstr	d19, [fp, #-748]
+	vstr	d16, [fp, #-772]
+	vstr	d17, [fp, #-764]
+	vldr	d18, [fp, #-756]
+	vldr	d19, [fp, #-748]
+	vldr	d16, [fp, #-772]
+	vldr	d17, [fp, #-764]
+	veor	q8, q9, q8
+	movw	r3, #61672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-788]
+	vstr	d19, [fp, #-780]
+	vstr	d16, [fp, #-804]
+	vstr	d17, [fp, #-796]
+	vldr	d18, [fp, #-788]
+	vldr	d19, [fp, #-780]
+	vldr	d16, [fp, #-804]
+	vldr	d17, [fp, #-796]
+	veor	q8, q9, q8
+	movw	r3, #61656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-820]
+	vstr	d19, [fp, #-812]
+	vstr	d16, [fp, #-836]
+	vstr	d17, [fp, #-828]
+	vldr	d18, [fp, #-820]
+	vldr	d19, [fp, #-812]
+	vldr	d16, [fp, #-836]
+	vldr	d17, [fp, #-828]
+	veor	q8, q9, q8
+	movw	r3, #61640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-852]
+	vstr	d19, [fp, #-844]
+	vstr	d16, [fp, #-868]
+	vstr	d17, [fp, #-860]
+	vldr	d18, [fp, #-852]
+	vldr	d19, [fp, #-844]
+	vldr	d16, [fp, #-868]
+	vldr	d17, [fp, #-860]
+	veor	q8, q9, q8
+	movw	r3, #61624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	movw	r2, #61672
+	movt	r2, 65535
+	sub	r1, fp, #4
+	add	r2, r1, r2
+	vldmia	r2, {d16-d17}
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r2, r3, #16
+	movw	r3, #61656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r2, r3, #32
+	movw	r3, #61640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r2, r3, #48
+	movw	r3, #61624
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r2, r3, #64
+	movw	r3, #61672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #20
+	vldmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #52
+	vldmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-884]
+	vstr	d19, [fp, #-876]
+	vstr	d16, [fp, #-900]
+	vstr	d17, [fp, #-892]
+	vldr	d16, [fp, #-884]
+	vldr	d17, [fp, #-876]
+	vldr	d18, [fp, #-900]
+	vldr	d19, [fp, #-892]
+	vadd.i32	q8, q8, q9
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov.i64	q9, #-4294967296  @ v4si
+	vstr	d18, [fp, #-20]
+	vstr	d19, [fp, #-12]
+	vstr	d16, [fp, #-916]
+	vstr	d17, [fp, #-908]
+	vldr	d16, [fp, #-20]
+	vldr	d17, [fp, #-12]
+	vstr	d16, [fp, #-932]
+	vstr	d17, [fp, #-924]
+	vldr	d18, [fp, #-916]
+	vldr	d19, [fp, #-908]
+	vldr	d16, [fp, #-932]
+	vldr	d17, [fp, #-924]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L75
+	vldr	d21, .L75+8
+	vstr	d20, [fp, #-36]
+	vstr	d21, [fp, #-28]
+	vstr	d16, [fp, #-948]
+	vstr	d17, [fp, #-940]
+	vldr	d16, [fp, #-36]
+	vldr	d17, [fp, #-28]
+	vstr	d16, [fp, #-964]
+	vstr	d17, [fp, #-956]
+	vldr	d20, [fp, #-948]
+	vldr	d21, [fp, #-940]
+	vldr	d16, [fp, #-964]
+	vldr	d17, [fp, #-956]
+	veor	q8, q10, q8
+	vstr	d18, [fp, #-980]
+	vstr	d19, [fp, #-972]
+	vstr	d16, [fp, #-996]
+	vstr	d17, [fp, #-988]
+	vldr	d16, [fp, #-980]
+	vldr	d17, [fp, #-972]
+	vldr	d18, [fp, #-996]
+	vldr	d19, [fp, #-988]
+	vadd.i32	q8, q8, q9
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #36
+	vldmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #4
+	vldmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L75+16
+	vldr	d19, .L75+24
+	vstr	d18, [fp, #-52]
+	vstr	d19, [fp, #-44]
+	vstr	d16, [fp, #-1012]
+	vstr	d17, [fp, #-1004]
+	mov	r3, #64512
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-52]
+	vldr	d17, [fp, #-44]
+	vstmia	r3, {d16-d17}
+	vldr	d18, [fp, #-1012]
+	vldr	d19, [fp, #-1004]
+	mov	r3, #64512
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L75+32
+	vldr	d21, .L75+40
+	vstr	d20, [fp, #-68]
+	vstr	d21, [fp, #-60]
+	movw	r3, #64496
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64480
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-68]
+	vldr	d17, [fp, #-60]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64496
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64480
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #64464
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #64448
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64464
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64448
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov.i64	q9, #-4294967296  @ v4si
+	vstr	d18, [fp, #-84]
+	vstr	d19, [fp, #-76]
+	movw	r3, #64432
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64416
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-84]
+	vldr	d17, [fp, #-76]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64432
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #64416
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L75
+	vldr	d21, .L75+8
+	vstr	d20, [fp, #-100]
+	vstr	d21, [fp, #-92]
+	movw	r3, #64400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64384
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-100]
+	vldr	d17, [fp, #-92]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64384
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #64368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #64352
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64352
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	b	.L76
+.L77:
+	.align	3
+.L75:
+	.word	-1
+	.word	0
+	.word	0
+	.word	0
+	.word	-1
+	.word	-1
+	.word	0
+	.word	0
+	.word	-1
+	.word	-1
+	.word	-1
+	.word	0
+	.word	0
+	.word	-1
+	.word	0
+	.word	0
+	.word	-1
+	.word	0
+	.word	0
+	.word	0
+.L76:
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #40
+	vldmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #56
+	vldmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #8
+	vldmia	r3, {d16-d17}
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #24
+	vldmia	r3, {d16-d17}
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L75+48
+	vldr	d19, .L75+56
+	vstr	d18, [fp, #-116]
+	vstr	d19, [fp, #-108]
+	movw	r3, #64336
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64320
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-116]
+	vldr	d17, [fp, #-108]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64336
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #64320
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov.i64	q10, #4294967295  @ v4si
+	vstr	d20, [fp, #-132]
+	vstr	d21, [fp, #-124]
+	movw	r3, #64304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64288
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-132]
+	vldr	d17, [fp, #-124]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64288
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #64272
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #64256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64272
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #64256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61672
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov.i64	q9, #-4294967296  @ v4si
+	vstr	d18, [fp, #-148]
+	vstr	d19, [fp, #-140]
+	movw	r3, #64240
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-148]
+	vldr	d17, [fp, #-140]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64240
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #64224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L75+64
+	vldr	d21, .L75+72
+	vstr	d20, [fp, #-164]
+	vstr	d21, [fp, #-156]
+	movw	r3, #64208
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-164]
+	vldr	d17, [fp, #-156]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64208
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #64176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #64160
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64160
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L78
+	vldr	d19, .L78+8
+	vstr	d18, [fp, #-180]
+	vstr	d19, [fp, #-172]
+	movw	r3, #64144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64128
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-180]
+	vldr	d17, [fp, #-172]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64144
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #64128
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L78+16
+	vldr	d21, .L78+24
+	vstr	d20, [fp, #-196]
+	vstr	d21, [fp, #-188]
+	movw	r3, #64112
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64096
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-196]
+	vldr	d17, [fp, #-188]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64112
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64096
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #64080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #64064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61640
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L78+32
+	vldr	d19, .L78+40
+	vstr	d18, [fp, #-212]
+	vstr	d19, [fp, #-204]
+	movw	r3, #64048
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64032
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-212]
+	vldr	d17, [fp, #-204]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64048
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #64032
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L78+48
+	vldr	d21, .L78+56
+	vstr	d20, [fp, #-228]
+	vstr	d21, [fp, #-220]
+	movw	r3, #64016
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #64000
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-228]
+	vldr	d17, [fp, #-220]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64016
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	mov	r3, #64000
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #63984
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63968
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63984
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63968
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61624
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63952
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63936
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63952
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63936
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	b	.L79
+.L80:
+	.align	3
+.L78:
+	.word	-1
+	.word	-1
+	.word	-1
+	.word	0
+	.word	0
+	.word	0
+	.word	-1
+	.word	-1
+	.word	-1
+	.word	0
+	.word	0
+	.word	-1
+	.word	0
+	.word	-1
+	.word	0
+	.word	0
+	.word	-1
+	.word	0
+	.word	-1
+	.word	-1
+	.word	2
+	.word	1
+	.word	2
+	.word	1
+.L79:
+	vldmia	r3, {d18-d19}
+	movw	r3, #61656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63920
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63904
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63920
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63904
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63888
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63888
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63856
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63840
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63856
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63840
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #28
+	vldmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #44
+	vldmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #60
+	vldmia	r3, {d16-d17}
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	sub	r3, fp, #3712
+	sub	r3, r3, #4
+	sub	r3, r3, #8
+	add	r3, r3, #12
+	vldmia	r3, {d16-d17}
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L78+64
+	vldr	d19, .L78+72
+	vstr	d18, [fp, #-244]
+	vstr	d19, [fp, #-236]
+	movw	r3, #63824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63808
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-244]
+	vldr	d17, [fp, #-236]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63824
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63808
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vldr	d18, .L78+80
+	vldr	d19, .L78+88
+	vstr	d18, [fp, #-260]
+	vstr	d19, [fp, #-252]
+	movw	r3, #63792
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63776
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-260]
+	vldr	d17, [fp, #-252]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63792
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63776
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L81
+	vldr	d19, .L81+8
+	vstr	d18, [fp, #-276]
+	vstr	d19, [fp, #-268]
+	movw	r3, #63760
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #63744
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-276]
+	vldr	d17, [fp, #-268]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63760
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	mov	r3, #63744
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vldr	d18, .L81+16
+	vldr	d19, .L81+24
+	vstr	d18, [fp, #-292]
+	vstr	d19, [fp, #-284]
+	movw	r3, #63728
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63712
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-292]
+	vldr	d17, [fp, #-284]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63728
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63712
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L81+32
+	vldr	d19, .L81+40
+	vstr	d18, [fp, #-308]
+	vstr	d19, [fp, #-300]
+	movw	r3, #63696
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63680
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-308]
+	vldr	d17, [fp, #-300]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63696
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63680
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vldr	d18, .L81+48
+	vldr	d19, .L81+56
+	vstr	d18, [fp, #-324]
+	vstr	d19, [fp, #-316]
+	movw	r3, #63664
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63648
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-324]
+	vldr	d17, [fp, #-316]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63664
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63648
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L81+64
+	vldr	d19, .L81+72
+	vstr	d18, [fp, #-340]
+	vstr	d19, [fp, #-332]
+	movw	r3, #63632
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63616
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-340]
+	vldr	d17, [fp, #-332]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63632
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63616
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vldr	d18, .L81+80
+	vldr	d19, .L81+88
+	vstr	d18, [fp, #-356]
+	vstr	d19, [fp, #-348]
+	movw	r3, #63600
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63584
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-356]
+	vldr	d17, [fp, #-348]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63600
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63584
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61624
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61672
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63568
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63568
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63552
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	b	.L82
+.L83:
+	.align	3
+.L81:
+	.word	-1
+	.word	0
+	.word	-1
+	.word	-1
+	.word	4
+	.word	3
+	.word	2
+	.word	2
+	.word	-1
+	.word	-1
+	.word	0
+	.word	-1
+	.word	3
+	.word	3
+	.word	2
+	.word	3
+	.word	-1
+	.word	-1
+	.word	0
+	.word	0
+	.word	3
+	.word	3
+	.word	0
+	.word	2
+	.word	-1
+	.word	-1
+	.word	-2
+	.word	-2
+	.word	3
+	.word	2
+	.word	1
+	.word	2
+	.word	4
+	.word	8
+	.word	12
+	.word	15
+.L82:
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61656
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63536
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63520
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63536
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63520
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63504
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	mov	r3, #63488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63504
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #63488
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63456
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63456
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L81+96
+	vldr	d19, .L81+104
+	vstr	d18, [fp, #-372]
+	vstr	d19, [fp, #-364]
+	movw	r3, #63440
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63424
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-372]
+	vldr	d17, [fp, #-364]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63440
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63424
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L81+112
+	vldr	d21, .L81+120
+	vstr	d20, [fp, #-388]
+	vstr	d21, [fp, #-380]
+	movw	r3, #63408
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63392
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-388]
+	vldr	d17, [fp, #-380]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63408
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63392
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #63376
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63360
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63376
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63360
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L81+128
+	vldr	d21, .L81+136
+	vstr	d20, [fp, #-404]
+	vstr	d21, [fp, #-396]
+	movw	r3, #63344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-404]
+	vldr	d17, [fp, #-396]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L84
+	vldr	d23, .L84+8
+	vstr	d22, [fp, #-420]
+	vstr	d23, [fp, #-412]
+	movw	r3, #63312
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63296
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-420]
+	vldr	d17, [fp, #-412]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63312
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63296
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #63280
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #63264
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63280
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #63264
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L84+16
+	vldr	d23, .L84+24
+	vstr	d22, [fp, #-436]
+	vstr	d23, [fp, #-428]
+	movw	r3, #63248
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #63232
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-436]
+	vldr	d17, [fp, #-428]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63248
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #63232
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L84+32
+	vldr	d25, .L84+40
+	vstr	d24, [fp, #-452]
+	vstr	d25, [fp, #-444]
+	movw	r3, #63216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-452]
+	vldr	d17, [fp, #-444]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #63184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #63168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #63168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #63152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #63136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #63136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #63120
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63104
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63120
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63104
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L84+48
+	vldr	d19, .L84+56
+	vstr	d18, [fp, #-468]
+	vstr	d19, [fp, #-460]
+	movw	r3, #63088
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63072
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-468]
+	vldr	d17, [fp, #-460]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63088
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63072
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #61720
+	movt	r3, 65535
+	b	.L85
+.L86:
+	.align	3
+.L84:
+	.word	-28
+	.word	-24
+	.word	-20
+	.word	-17
+	.word	19
+	.word	23
+	.word	25
+	.word	29
+	.word	-13
+	.word	-9
+	.word	-7
+	.word	-3
+	.word	-1
+	.word	-1
+	.word	-1
+	.word	-2
+	.word	0
+	.word	3
+	.word	2
+	.word	1
+	.word	0
+	.word	4
+	.word	8
+	.word	12
+	.word	0
+	.word	-28
+	.word	-24
+	.word	-20
+	.word	0
+	.word	19
+	.word	23
+	.word	25
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-7
+.L85:
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L84+64
+	vldr	d21, .L84+72
+	vstr	d20, [fp, #-484]
+	vstr	d21, [fp, #-476]
+	movw	r3, #63056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63040
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-484]
+	vldr	d17, [fp, #-476]
+	vstmia	r3, {d16-d17}
+	movw	r3, #63056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63040
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #63024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63008
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63008
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L84+80
+	vldr	d21, .L84+88
+	vstr	d20, [fp, #-500]
+	vstr	d21, [fp, #-492]
+	movw	r3, #62992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #62976
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-500]
+	vldr	d17, [fp, #-492]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #62976
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L84+96
+	vldr	d23, .L84+104
+	vstr	d22, [fp, #-516]
+	vstr	d23, [fp, #-508]
+	movw	r3, #62960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-516]
+	vldr	d17, [fp, #-508]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #62928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #62912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L84+112
+	vldr	d23, .L84+120
+	vstr	d22, [fp, #-532]
+	vstr	d23, [fp, #-524]
+	movw	r3, #62896
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62880
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-532]
+	vldr	d17, [fp, #-524]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62896
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62880
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L84+128
+	vldr	d25, .L84+136
+	vstr	d24, [fp, #-548]
+	vstr	d25, [fp, #-540]
+	movw	r3, #62864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-548]
+	vldr	d17, [fp, #-540]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62864
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #62832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #62816
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #62816
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #62800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #62784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #62768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L87
+	vldr	d19, .L87+8
+	vstr	d18, [fp, #-564]
+	vstr	d19, [fp, #-556]
+	movw	r3, #62736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	mov	r3, #62720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-564]
+	vldr	d17, [fp, #-556]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62736
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	mov	r3, #62720
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L87+16
+	vldr	d21, .L87+24
+	vstr	d20, [fp, #-580]
+	vstr	d21, [fp, #-572]
+	movw	r3, #62704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-580]
+	vldr	d17, [fp, #-572]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62672
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62672
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62656
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L87+32
+	vldr	d21, .L87+40
+	vstr	d20, [fp, #-596]
+	vstr	d21, [fp, #-588]
+	movw	r3, #62640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-596]
+	vldr	d17, [fp, #-588]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62640
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62624
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L87+48
+	vldr	d23, .L87+56
+	vstr	d22, [fp, #-612]
+	vstr	d23, [fp, #-604]
+	movw	r3, #62608
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62592
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-612]
+	vldr	d17, [fp, #-604]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62608
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62592
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #62576
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62560
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62576
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #62560
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L87+64
+	vldr	d23, .L87+72
+	vstr	d22, [fp, #-628]
+	vstr	d23, [fp, #-620]
+	movw	r3, #62544
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62528
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-628]
+	vldr	d17, [fp, #-620]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62544
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62528
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L87+80
+	vldr	d25, .L87+88
+	vstr	d24, [fp, #-644]
+	vstr	d25, [fp, #-636]
+	movw	r3, #62512
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62496
+	movt	r3, 65535
+	sub	r1, fp, #4
+	b	.L88
+.L89:
+	.align	3
+.L87:
+	.word	-2
+	.word	-1
+	.word	-1
+	.word	-1
+	.word	2
+	.word	0
+	.word	3
+	.word	2
+	.word	15
+	.word	0
+	.word	4
+	.word	8
+	.word	-17
+	.word	0
+	.word	-28
+	.word	-24
+	.word	29
+	.word	0
+	.word	19
+	.word	23
+	.word	-3
+	.word	0
+	.word	-13
+	.word	-9
+	.word	-2
+	.word	-2
+	.word	-1
+	.word	-1
+	.word	1
+	.word	2
+	.word	0
+	.word	3
+	.word	12
+	.word	15
+	.word	0
+	.word	4
+	.word	-20
+	.word	-17
+	.word	0
+	.word	-28
+.L88:
+	add	r3, r1, r3
+	vldr	d16, [fp, #-644]
+	vldr	d17, [fp, #-636]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62512
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62496
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #62480
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d22-d23}
+	mov	r3, #62464
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62480
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	mov	r3, #62464
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #62448
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62432
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62448
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #62432
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #62416
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62416
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62400
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L87+96
+	vldr	d19, .L87+104
+	vstr	d18, [fp, #-660]
+	vstr	d19, [fp, #-652]
+	movw	r3, #62384
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-660]
+	vldr	d17, [fp, #-652]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62384
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62368
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L87+112
+	vldr	d21, .L87+120
+	vstr	d20, [fp, #-676]
+	vstr	d21, [fp, #-668]
+	movw	r3, #62352
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62336
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-676]
+	vldr	d17, [fp, #-668]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62352
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62336
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #62320
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62320
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62304
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L87+128
+	vldr	d21, .L87+136
+	vstr	d20, [fp, #-692]
+	vstr	d21, [fp, #-684]
+	movw	r3, #62288
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-692]
+	vldr	d17, [fp, #-684]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62288
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62272
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	vmov	q10, q8  @ v4si
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L87+144
+	vldr	d23, .L87+152
+	vstr	d22, [fp, #-708]
+	vstr	d23, [fp, #-700]
+	movw	r3, #62256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62240
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-708]
+	vldr	d17, [fp, #-700]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62256
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62240
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	movw	r3, #62224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	mov	r3, #62208
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62224
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	mov	r3, #62208
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L90
+	vldr	d23, .L90+8
+	vstr	d22, [fp, #-724]
+	vstr	d23, [fp, #-716]
+	movw	r3, #62192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-724]
+	vldr	d17, [fp, #-716]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62192
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62176
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d24, .L90+16
+	vldr	d25, .L90+24
+	vstr	d24, [fp, #-740]
+	vstr	d25, [fp, #-732]
+	movw	r3, #62160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-740]
+	vldr	d17, [fp, #-732]
+	vstmia	r3, {d16-d17}
+	movw	r3, #62160
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62144
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d24-d25}
+	vshl.u32	q8, q8, q12
+	movw	r3, #62128
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #62112
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62128
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #62112
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #62096
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #62080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62096
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #62080
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	movw	r3, #62064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #62048
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62064
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #62048
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #4
+	vldmia	r3, {d16-d17}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #20
+	vldmia	r3, {d16-d17}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #36
+	vldmia	r3, {d16-d17}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	add	r3, r3, #52
+	vldmia	r3, {d16-d17}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-3924]
+	ldr	r2, [r3, #0]
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	str	r2, [fp, #-3496]
+	movw	r3, #62024
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r2, [fp, #-3496]
+	movw	r3, #62024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vmov.32	d17[1], r2
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61736
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #62008
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #62008
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61992
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	b	.L91
+.L92:
+	.align	3
+.L90:
+	.word	25
+	.word	29
+	.word	0
+	.word	19
+	.word	-7
+	.word	-3
+	.word	0
+	.word	-13
+.L91:
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61720
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61704
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61928
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61928
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #61688
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #61896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #61912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #61896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r2, [fp, #-3920]
+	movw	r3, #61800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	ldr	r3, [fp, #-3920]
+	add	r2, r3, #16
+	movw	r3, #61784
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	ldr	r3, [fp, #-3920]
+	add	r2, r3, #32
+	movw	r3, #61768
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	ldr	r3, [fp, #-3920]
+	add	r2, r3, #48
+	movw	r3, #61752
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	add	sp, fp, #0
+	ldmfd	sp!, {fp}
+	bx	lr
+	.size	bmw_small_f0, .-bmw_small_f0
+	.align	2
+	.type	bmw_small_f2, %function
+bmw_small_f2:
+	@ args = 0, pretend = 0, frame = 1752
+	@ frame_needed = 1, uses_anonymous_args = 0
+	@ link register save eliminated.
+	str	fp, [sp, #-4]!
+	add	fp, sp, #0
+	sub	sp, sp, #1744
+	sub	sp, sp, #12
+	str	r0, [fp, #-1744]
+	str	r1, [fp, #-1748]
+	str	r2, [fp, #-1752]
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #64
+	vldmia	r3, {d16-d17}
+	movw	r3, #63928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #80
+	vldmia	r3, {d16-d17}
+	movw	r3, #63912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #96
+	vldmia	r3, {d16-d17}
+	movw	r3, #63896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #112
+	vldmia	r3, {d16-d17}
+	movw	r3, #63880
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-180]
+	vstr	d19, [fp, #-172]
+	vstr	d16, [fp, #-196]
+	vstr	d17, [fp, #-188]
+	vldr	d18, [fp, #-180]
+	vldr	d19, [fp, #-172]
+	vldr	d16, [fp, #-196]
+	vldr	d17, [fp, #-188]
+	veor	q8, q9, q8
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63896
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #63880
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-212]
+	vstr	d19, [fp, #-204]
+	vstr	d16, [fp, #-228]
+	vstr	d17, [fp, #-220]
+	vldr	d18, [fp, #-212]
+	vldr	d19, [fp, #-204]
+	vldr	d16, [fp, #-228]
+	vldr	d17, [fp, #-220]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-244]
+	vstr	d19, [fp, #-236]
+	vstr	d16, [fp, #-260]
+	vstr	d17, [fp, #-252]
+	vldr	d18, [fp, #-244]
+	vldr	d19, [fp, #-236]
+	vldr	d16, [fp, #-260]
+	vldr	d17, [fp, #-252]
+	veor	q8, q9, q8
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d16, [fp, #-276]
+	vstr	d17, [fp, #-268]
+	vldr	d16, [fp, #-276]
+	vldr	d17, [fp, #-268]
+	vmov	d18, d16  @ v2si
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d16, [fp, #-292]
+	vstr	d17, [fp, #-284]
+	vldr	d16, [fp, #-292]
+	vldr	d17, [fp, #-284]
+	vmov	d16, d17
+	fstd	d18, [fp, #-300]
+	fstd	d16, [fp, #-308]
+	fldd	d17, [fp, #-300]
+	fldd	d16, [fp, #-308]
+	veor	d16, d17, d16
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d17, [r3, #0]
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fldd	d16, [r3, #0]
+	fstd	d16, [fp, #-316]
+	fldd	d16, [fp, #-316]
+	fmrrd	r2, r3, d16	@ int
+	str	r2, [fp, #-324]
+	str	r3, [fp, #-320]
+	fldd	d16, [fp, #-324]	@ int
+	vshr.u64	d16, d16, #32
+	fmrrd	r2, r3, d16	@ int
+	str	r2, [fp, #-332]
+	str	r3, [fp, #-328]
+	fldd	d16, [fp, #-332]	@ int
+	fstd	d17, [fp, #-340]
+	fstd	d16, [fp, #-348]
+	fldd	d17, [fp, #-340]
+	fldd	d16, [fp, #-348]
+	veor	d16, d17, d16
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fldd	d16, [r3, #0]
+	fstd	d16, [fp, #-356]
+	fldd	d16, [fp, #-356]
+	vdup.32	q8, d16[0]
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d16, [fp, #-372]
+	vstr	d17, [fp, #-364]
+	vldr	d16, [fp, #-372]
+	vldr	d17, [fp, #-364]
+	vmov	d18, d16  @ v2si
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d16, [fp, #-388]
+	vstr	d17, [fp, #-380]
+	vldr	d16, [fp, #-388]
+	vldr	d17, [fp, #-380]
+	vmov	d16, d17
+	fstd	d18, [fp, #-396]
+	fstd	d16, [fp, #-404]
+	fldd	d17, [fp, #-396]
+	fldd	d16, [fp, #-404]
+	veor	d16, d17, d16
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fldd	d17, [r3, #0]
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fldd	d16, [r3, #0]
+	fstd	d16, [fp, #-412]
+	fldd	d16, [fp, #-412]
+	fmrrd	r2, r3, d16	@ int
+	str	r2, [fp, #-420]
+	str	r3, [fp, #-416]
+	fldd	d16, [fp, #-420]	@ int
+	vshr.u64	d16, d16, #32
+	fmrrd	r2, r3, d16	@ int
+	str	r2, [fp, #-428]
+	str	r3, [fp, #-424]
+	fldd	d16, [fp, #-428]	@ int
+	fstd	d17, [fp, #-436]
+	fstd	d16, [fp, #-444]
+	fldd	d17, [fp, #-436]
+	fldd	d16, [fp, #-444]
+	veor	d16, d17, d16
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	fstd	d16, [r3, #0]
+	movw	r3, #63872
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	fldd	d16, [r3, #0]
+	fstd	d16, [fp, #-452]
+	fldd	d16, [fp, #-452]
+	vdup.32	q8, d16[0]
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L94
+	vldr	d19, .L94+8
+	vstr	d18, [fp, #-20]
+	vstr	d19, [fp, #-12]
+	vstr	d16, [fp, #-468]
+	vstr	d17, [fp, #-460]
+	vldr	d16, [fp, #-20]
+	vldr	d17, [fp, #-12]
+	vstr	d16, [fp, #-484]
+	vstr	d17, [fp, #-476]
+	vldr	d16, [fp, #-468]
+	vldr	d17, [fp, #-460]
+	vldr	d18, [fp, #-484]
+	vldr	d19, [fp, #-476]
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #63928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L94+16
+	vldr	d21, .L94+24
+	vstr	d20, [fp, #-36]
+	vstr	d21, [fp, #-28]
+	vstr	d16, [fp, #-500]
+	vstr	d17, [fp, #-492]
+	vldr	d16, [fp, #-36]
+	vldr	d17, [fp, #-28]
+	vstr	d16, [fp, #-516]
+	vstr	d17, [fp, #-508]
+	vldr	d16, [fp, #-500]
+	vldr	d17, [fp, #-492]
+	vldr	d20, [fp, #-516]
+	vldr	d21, [fp, #-508]
+	vshl.u32	q8, q8, q10
+	vstr	d18, [fp, #-532]
+	vstr	d19, [fp, #-524]
+	vstr	d16, [fp, #-548]
+	vstr	d17, [fp, #-540]
+	vldr	d18, [fp, #-532]
+	vldr	d19, [fp, #-524]
+	vldr	d16, [fp, #-548]
+	vldr	d17, [fp, #-540]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	ldr	r3, [fp, #-1752]
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-564]
+	vstr	d19, [fp, #-556]
+	vstr	d16, [fp, #-580]
+	vstr	d17, [fp, #-572]
+	vldr	d18, [fp, #-564]
+	vldr	d19, [fp, #-556]
+	vldr	d16, [fp, #-580]
+	vldr	d17, [fp, #-572]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #63896
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstr	d20, [fp, #-596]
+	vstr	d21, [fp, #-588]
+	vstr	d16, [fp, #-612]
+	vstr	d17, [fp, #-604]
+	vldr	d20, [fp, #-596]
+	vldr	d21, [fp, #-588]
+	vldr	d16, [fp, #-612]
+	vldr	d17, [fp, #-604]
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	ldr	r3, [fp, #-1748]
+	vldmia	r3, {d16-d17}
+	vstr	d20, [fp, #-628]
+	vstr	d21, [fp, #-620]
+	vstr	d16, [fp, #-644]
+	vstr	d17, [fp, #-636]
+	vldr	d20, [fp, #-628]
+	vldr	d21, [fp, #-620]
+	vldr	d16, [fp, #-644]
+	vldr	d17, [fp, #-636]
+	veor	q8, q10, q8
+	vstr	d18, [fp, #-660]
+	vstr	d19, [fp, #-652]
+	vstr	d16, [fp, #-676]
+	vstr	d17, [fp, #-668]
+	vldr	d16, [fp, #-660]
+	vldr	d17, [fp, #-652]
+	vldr	d18, [fp, #-676]
+	vldr	d19, [fp, #-668]
+	vadd.i32	q8, q8, q9
+	movw	r3, #63848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L94+32
+	vldr	d19, .L94+40
+	vstr	d18, [fp, #-52]
+	vstr	d19, [fp, #-44]
+	vstr	d16, [fp, #-692]
+	vstr	d17, [fp, #-684]
+	vldr	d16, [fp, #-52]
+	vldr	d17, [fp, #-44]
+	vstr	d16, [fp, #-708]
+	vstr	d17, [fp, #-700]
+	vldr	d16, [fp, #-692]
+	vldr	d17, [fp, #-684]
+	vldr	d18, [fp, #-708]
+	vldr	d19, [fp, #-700]
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #63912
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L94+48
+	vldr	d21, .L94+56
+	vstr	d20, [fp, #-68]
+	vstr	d21, [fp, #-60]
+	vstr	d16, [fp, #-724]
+	vstr	d17, [fp, #-716]
+	vldr	d16, [fp, #-68]
+	vldr	d17, [fp, #-60]
+	vstr	d16, [fp, #-740]
+	vstr	d17, [fp, #-732]
+	vldr	d16, [fp, #-724]
+	vldr	d17, [fp, #-716]
+	vldr	d20, [fp, #-740]
+	vldr	d21, [fp, #-732]
+	vshl.u32	q8, q8, q10
+	vstr	d18, [fp, #-756]
+	vstr	d19, [fp, #-748]
+	vstr	d16, [fp, #-772]
+	vstr	d17, [fp, #-764]
+	vldr	d18, [fp, #-756]
+	vldr	d19, [fp, #-748]
+	vldr	d16, [fp, #-772]
+	vldr	d17, [fp, #-764]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	ldr	r3, [fp, #-1752]
+	add	r3, r3, #16
+	vldmia	r3, {d16-d17}
+	vstr	d18, [fp, #-788]
+	vstr	d19, [fp, #-780]
+	vstr	d16, [fp, #-804]
+	vstr	d17, [fp, #-796]
+	vldr	d18, [fp, #-788]
+	vldr	d19, [fp, #-780]
+	vldr	d16, [fp, #-804]
+	vldr	d17, [fp, #-796]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #63880
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vstr	d20, [fp, #-820]
+	vstr	d21, [fp, #-812]
+	vstr	d16, [fp, #-836]
+	vstr	d17, [fp, #-828]
+	vldr	d20, [fp, #-820]
+	vldr	d21, [fp, #-812]
+	vldr	d16, [fp, #-836]
+	vldr	d17, [fp, #-828]
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #16
+	vldmia	r3, {d16-d17}
+	vstr	d20, [fp, #-852]
+	vstr	d21, [fp, #-844]
+	vstr	d16, [fp, #-868]
+	vstr	d17, [fp, #-860]
+	vldr	d20, [fp, #-852]
+	vldr	d21, [fp, #-844]
+	vldr	d16, [fp, #-868]
+	vldr	d17, [fp, #-860]
+	veor	q8, q10, q8
+	vstr	d18, [fp, #-884]
+	vstr	d19, [fp, #-876]
+	vstr	d16, [fp, #-900]
+	vstr	d17, [fp, #-892]
+	vldr	d16, [fp, #-884]
+	vldr	d17, [fp, #-876]
+	vldr	d18, [fp, #-900]
+	vldr	d19, [fp, #-892]
+	vadd.i32	q8, q8, q9
+	movw	r3, #63832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #60
+	vldmia	r3, {d16-d17}
+	movw	r3, #63928
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #92
+	ldr	r2, [r3, #0]
+	movw	r3, #63928
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	str	r2, [fp, #-904]
+	vstr	d16, [fp, #-924]
+	vstr	d17, [fp, #-916]
+	ldr	r3, [fp, #-904]
+	vldr	d16, [fp, #-924]
+	vldr	d17, [fp, #-916]
+	vmov.32	d16[0], r3
+	movw	r3, #63928
+	b	.L95
+.L96:
+	.align	3
+.L94:
+	.word	5
+	.word	-7
+	.word	-5
+	.word	-1
+	.word	-5
+	.word	8
+	.word	5
+	.word	5
+	.word	-3
+	.word	6
+	.word	-4
+	.word	-11
+	.word	0
+	.word	-6
+	.word	6
+	.word	2
+	.word	9
+	.word	10
+	.word	11
+	.word	12
+	.word	-23
+	.word	-22
+	.word	-21
+	.word	-20
+	.word	8
+	.word	-6
+	.word	6
+	.word	4
+.L95:
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L94+64
+	vldr	d19, .L94+72
+	vstr	d18, [fp, #-84]
+	vstr	d19, [fp, #-76]
+	vstr	d16, [fp, #-940]
+	vstr	d17, [fp, #-932]
+	vldr	d16, [fp, #-84]
+	vldr	d17, [fp, #-76]
+	vstr	d16, [fp, #-956]
+	vstr	d17, [fp, #-948]
+	vldr	d16, [fp, #-940]
+	vldr	d17, [fp, #-932]
+	vldr	d18, [fp, #-956]
+	vldr	d19, [fp, #-948]
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #63832
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L94+80
+	vldr	d21, .L94+88
+	vstr	d20, [fp, #-100]
+	vstr	d21, [fp, #-92]
+	vstr	d16, [fp, #-972]
+	vstr	d17, [fp, #-964]
+	vldr	d16, [fp, #-100]
+	vldr	d17, [fp, #-92]
+	vstr	d16, [fp, #-988]
+	vstr	d17, [fp, #-980]
+	vldr	d16, [fp, #-972]
+	vldr	d17, [fp, #-964]
+	vldr	d20, [fp, #-988]
+	vldr	d21, [fp, #-980]
+	vshl.u32	q8, q8, q10
+	vstr	d18, [fp, #-1004]
+	vstr	d19, [fp, #-996]
+	vstr	d16, [fp, #-1020]
+	vstr	d17, [fp, #-1012]
+	vldr	d18, [fp, #-1004]
+	vldr	d19, [fp, #-996]
+	vldr	d16, [fp, #-1020]
+	vldr	d17, [fp, #-1012]
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #63896
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	ldr	r3, [fp, #-1752]
+	add	r3, r3, #32
+	vldmia	r3, {d16-d17}
+	movw	r3, #64504
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #64488
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64504
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #64488
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #64472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #64456
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64472
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64456
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L94+96
+	vldr	d23, .L94+104
+	vstr	d22, [fp, #-116]
+	vstr	d23, [fp, #-108]
+	movw	r3, #64440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64424
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-116]
+	vldr	d17, [fp, #-108]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64440
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64424
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	movw	r3, #63928
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d24-d25}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #32
+	vldmia	r3, {d16-d17}
+	movw	r3, #64408
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d24-d25}
+	movw	r3, #64392
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64408
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d24-d25}
+	movw	r3, #64392
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q12, q8
+	movw	r3, #64376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #64360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64376
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #64360
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #64344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #64328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64344
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64328
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vadd.i32	q8, q8, q10
+	movw	r3, #64312
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #64296
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64312
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64296
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #63816
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63848
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d18, .L97
+	vldr	d19, .L97+8
+	vstr	d18, [fp, #-132]
+	vstr	d19, [fp, #-124]
+	movw	r3, #64280
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64264
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-132]
+	vldr	d17, [fp, #-124]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64280
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64264
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vshl.u32	q8, q8, q9
+	vmov	q9, q8  @ v4si
+	movw	r3, #63848
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vldr	d20, .L97+16
+	vldr	d21, .L97+24
+	vstr	d20, [fp, #-148]
+	vstr	d21, [fp, #-140]
+	movw	r3, #64248
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64232
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldr	d16, [fp, #-148]
+	vldr	d17, [fp, #-140]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64248
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64232
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d20-d21}
+	vshl.u32	q8, q8, q10
+	movw	r3, #64216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #64200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64216
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	movw	r3, #64200
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q9, q8
+	vmov	q9, q8  @ v4si
+	movw	r3, #63944
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #63880
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	ldr	r3, [fp, #-1752]
+	add	r3, r3, #48
+	vldmia	r3, {d16-d17}
+	movw	r3, #64184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #64168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64184
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #64168
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #64152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #64136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64152
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	movw	r3, #64136
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q10, q8
+	vmov	q10, q8  @ v4si
+	movw	r3, #63960
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	vldr	d22, .L97+32
+	vldr	d23, .L97+40
+	vstr	d22, [fp, #-164]
+	vstr	d23, [fp, #-156]
+	movw	r3, #64120
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64104
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldr	d16, [fp, #-164]
+	vldr	d17, [fp, #-156]
+	vstmia	r3, {d16-d17}
+	movw	r3, #64120
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64104
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d22-d23}
+	vshl.u32	q8, q8, q11
+	vmov	q11, q8  @ v4si
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #76
+	vldmia	r3, {d24-d25}
+	ldr	r3, [fp, #-1748]
+	add	r3, r3, #48
+	vldmia	r3, {d16-d17}
+	movw	r3, #64088
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d24-d25}
+	movw	r3, #64072
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64088
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d24-d25}
+	movw	r3, #64072
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q12, q8
+	movw	r3, #64056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d22-d23}
+	movw	r3, #64040
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64056
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d22-d23}
+	movw	r3, #64040
+	movt	r3, 65535
+	b	.L98
+.L99:
+	.align	3
+.L97:
+	.word	13
+	.word	14
+	.word	15
+	.word	16
+	.word	-19
+	.word	-18
+	.word	-17
+	.word	-16
+	.word	-3
+	.word	-4
+	.word	-7
+	.word	-2
+.L98:
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d16-d17}
+	veor	q8, q11, q8
+	movw	r3, #64024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d20-d21}
+	movw	r3, #64008
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #64024
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #64008
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d20-d21}
+	vadd.i32	q8, q8, q10
+	movw	r3, #63992
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d18-d19}
+	movw	r3, #63976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vstmia	r3, {d16-d17}
+	movw	r3, #63992
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	movw	r3, #63976
+	movt	r3, 65535
+	sub	r2, fp, #4
+	add	r3, r2, r3
+	vldmia	r3, {d18-d19}
+	vadd.i32	q8, q8, q9
+	movw	r3, #63800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vstmia	r3, {d16-d17}
+	ldr	r2, [fp, #-1744]
+	movw	r3, #63848
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	ldr	r3, [fp, #-1744]
+	add	r2, r3, #16
+	movw	r3, #63832
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	ldr	r3, [fp, #-1744]
+	add	r2, r3, #32
+	movw	r3, #63816
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	ldr	r3, [fp, #-1744]
+	add	r2, r3, #48
+	movw	r3, #63800
+	movt	r3, 65535
+	sub	r1, fp, #4
+	add	r3, r1, r3
+	vldmia	r3, {d16-d17}
+	vstmia	r2, {d16-d17}
+	add	sp, fp, #0
+	ldmfd	sp!, {fp}
+	bx	lr
+	.size	bmw_small_f2, .-bmw_small_f2
+	.align	2
+	.global	bmw_small_nextBlock
+	.type	bmw_small_nextBlock, %function
+bmw_small_nextBlock:
+	@ args = 0, pretend = 0, frame = 136
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #136
+	str	r0, [fp, #-136]
+	str	r1, [fp, #-140]
+	ldr	r2, [fp, #-136]
+	ldr	r3, [fp, #-140]
+	sub	r1, fp, #132
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	bl	bmw_small_f0
+	ldr	r2, [fp, #-140]
+	ldr	r3, [fp, #-136]
+	sub	r1, fp, #132
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	bl	bmw_small_f1
+	ldr	r1, [fp, #-136]
+	ldr	r3, [fp, #-140]
+	sub	r2, fp, #132
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	bl	bmw_small_f2
+	ldr	r3, [fp, #-136]
+	ldr	r3, [r3, #64]
+	add	r2, r3, #1
+	ldr	r3, [fp, #-136]
+	str	r2, [r3, #64]
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw_small_nextBlock, .-bmw_small_nextBlock
+	.align	2
+	.global	bmw_small_lastBlock
+	.type	bmw_small_lastBlock, %function
+bmw_small_lastBlock:
+	@ args = 0, pretend = 0, frame = 216
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {r4, r5, fp, lr}
+	add	fp, sp, #12
+	sub	sp, sp, #216
+	str	r0, [fp, #-216]
+	str	r1, [fp, #-220]
+	mov	r3, r2
+	strh	r3, [fp, #-222]	@ movhi
+	b	.L102
+.L103:
+	ldr	r0, [fp, #-216]
+	ldr	r1, [fp, #-220]
+	bl	bmw_small_nextBlock
+	ldrh	r3, [fp, #-222]	@ movhi
+	sub	r3, r3, #512
+	strh	r3, [fp, #-222]	@ movhi
+	ldr	r3, [fp, #-220]
+	add	r3, r3, #64
+	str	r3, [fp, #-220]
+.L102:
+	ldrh	r2, [fp, #-222]
+	movw	r3, #511
+	cmp	r2, r3
+	bhi	.L103
+	sub	r3, fp, #80
+	mov	r0, r3
+	mov	r1, #0
+	mov	r2, #64
+	bl	memset
+	ldrh	r3, [fp, #-222]
+	add	r3, r3, #7
+	add	r2, r3, #7
+	cmp	r3, #0
+	movlt	r3, r2
+	mov	r3, r3, asr #3
+	sub	r2, fp, #80
+	mov	r0, r2
+	ldr	r1, [fp, #-220]
+	mov	r2, r3
+	bl	memcpy
+	ldrh	r3, [fp, #-222]
+	mov	r3, r3, lsr #3
+	uxth	r3, r3
+	mov	r1, r3
+	ldrh	r3, [fp, #-222]
+	mov	r3, r3, lsr #3
+	uxth	r3, r3
+	mov	r2, r3
+	mvn	r3, #67
+	sub	r0, fp, #12
+	add	r2, r0, r2
+	add	r3, r2, r3
+	ldrb	r3, [r3, #0]	@ zero_extendqisi2
+	uxtb	r2, r3
+	ldrh	r3, [fp, #-222]
+	and	r3, r3, #7
+	mov	r0, #128
+	mov	r3, r0, asr r3
+	uxtb	r3, r3
+	orr	r3, r2, r3
+	uxtb	r3, r3
+	uxtb	r2, r3
+	mvn	r3, #67
+	sub	r0, fp, #12
+	add	r1, r0, r1
+	add	r3, r1, r3
+	strb	r2, [r3, #0]
+	ldrh	r3, [fp, #-222]
+	add	r3, r3, #1
+	cmp	r3, #448
+	ble	.L104
+	sub	r3, fp, #80
+	ldr	r0, [fp, #-216]
+	mov	r1, r3
+	bl	bmw_small_nextBlock
+	sub	r3, fp, #80
+	mov	r0, r3
+	mov	r1, #0
+	mov	r2, #56
+	bl	memset
+	ldr	r3, [fp, #-216]
+	ldr	r3, [r3, #64]
+	sub	r2, r3, #1
+	ldr	r3, [fp, #-216]
+	str	r2, [r3, #64]
+.L104:
+	sub	r3, fp, #80
+	add	ip, r3, #56
+	ldr	r3, [fp, #-216]
+	ldr	r3, [r3, #64]
+	mov	r2, r3
+	mov	r3, #0
+	mov	r1, r2, lsr #23
+	mov	r5, r3, asl #9
+	orr	r5, r1, r5
+	mov	r4, r2, asl #9
+	mov	r0, r4
+	mov	r1, r5
+	ldrh	r3, [fp, #-222]
+	mov	r2, r3
+	mov	r3, #0
+	adds	r2, r2, r0
+	adc	r3, r3, r1
+	strd	r2, [ip]
+	sub	r3, fp, #80
+	ldr	r0, [fp, #-216]
+	mov	r1, r3
+	bl	bmw_small_nextBlock
+	sub	r3, fp, #80
+	mov	r0, r3
+	mov	r1, #170
+	mov	r2, #64
+	bl	memset
+	mov	r3, #0
+	strb	r3, [fp, #-13]
+	b	.L105
+.L106:
+	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
+	mov	r1, r3, asl #2
+	ldrb	r3, [fp, #-13]
+	sub	r3, r3, #96
+	uxtb	r2, r3
+	mvn	r3, #67
+	sub	r0, fp, #12
+	add	r1, r0, r1
+	add	r3, r1, r3
+	strb	r2, [r3, #0]
+	ldrb	r3, [fp, #-13]
+	add	r3, r3, #1
+	strb	r3, [fp, #-13]
+.L105:
+	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
+	cmp	r3, #15
+	bls	.L106
+	sub	r2, fp, #80
+	ldr	r3, [fp, #-216]
+	sub	r1, fp, #208
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	bl	bmw_small_f0
+	ldr	r2, [fp, #-216]
+	sub	r3, fp, #80
+	sub	r1, fp, #208
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	bl	bmw_small_f1
+	sub	r1, fp, #80
+	ldr	r3, [fp, #-216]
+	sub	r2, fp, #208
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	bl	bmw_small_f2
+	ldr	r2, [fp, #-216]
+	sub	r3, fp, #80
+	mov	r0, r2
+	mov	r1, r3
+	mov	r2, #64
+	bl	memcpy
+	sub	sp, fp, #12
+	ldmfd	sp!, {r4, r5, fp, pc}
+	.size	bmw_small_lastBlock, .-bmw_small_lastBlock
+	.align	2
+	.global	bmw224_init
+	.type	bmw224_init, %function
+bmw224_init:
+	@ args = 0, pretend = 0, frame = 16
+	@ frame_needed = 1, uses_anonymous_args = 0
+	@ link register save eliminated.
+	str	fp, [sp, #-4]!
+	add	fp, sp, #0
+	sub	sp, sp, #20
+	str	r0, [fp, #-16]
+	ldr	r2, [fp, #-16]
+	movw	r3, #515
+	movt	r3, 1
+	str	r3, [r2, #0]
+	mov	r3, #1
+	strb	r3, [fp, #-5]
+	b	.L108
+.L109:
+	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
+	ldrb	r3, [fp, #-5]	@ zero_extendqisi2
+	sub	r2, r3, #1
+	ldr	r3, [fp, #-16]
+	ldr	r2, [r3, r2, asl #2]
+	movw	r3, #1028
+	movt	r3, 1028
+	add	r3, r2, r3
+	ldr	r2, [fp, #-16]
+	str	r3, [r2, r1, asl #2]
+	ldrb	r3, [fp, #-5]
+	add	r3, r3, #1
+	strb	r3, [fp, #-5]
+.L108:
+	ldrb	r3, [fp, #-5]	@ zero_extendqisi2
+	cmp	r3, #15
+	bls	.L109
+	ldr	r3, [fp, #-16]
+	mov	r2, #0
+	str	r2, [r3, #64]
+	add	sp, fp, #0
+	ldmfd	sp!, {fp}
+	bx	lr
+	.size	bmw224_init, .-bmw224_init
+	.align	2
+	.global	bmw256_init
+	.type	bmw256_init, %function
+bmw256_init:
+	@ args = 0, pretend = 0, frame = 16
+	@ frame_needed = 1, uses_anonymous_args = 0
+	@ link register save eliminated.
+	str	fp, [sp, #-4]!
+	add	fp, sp, #0
+	sub	sp, sp, #20
+	str	r0, [fp, #-16]
+	ldr	r2, [fp, #-16]
+	movw	r3, #16963
+	movt	r3, 16449
+	str	r3, [r2, #0]
+	mov	r3, #1
+	strb	r3, [fp, #-5]
+	b	.L111
+.L112:
+	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
+	ldrb	r3, [fp, #-5]	@ zero_extendqisi2
+	sub	r2, r3, #1
+	ldr	r3, [fp, #-16]
+	ldr	r2, [r3, r2, asl #2]
+	movw	r3, #1028
+	movt	r3, 1028
+	add	r3, r2, r3
+	ldr	r2, [fp, #-16]
+	str	r3, [r2, r1, asl #2]
+	ldrb	r3, [fp, #-5]
+	add	r3, r3, #1
+	strb	r3, [fp, #-5]
+.L111:
+	ldrb	r3, [fp, #-5]	@ zero_extendqisi2
+	cmp	r3, #15
+	bls	.L112
+	ldr	r3, [fp, #-16]
+	mov	r2, #0
+	str	r2, [r3, #64]
+	add	sp, fp, #0
+	ldmfd	sp!, {fp}
+	bx	lr
+	.size	bmw256_init, .-bmw256_init
+	.align	2
+	.global	bmw224_nextBlock
+	.type	bmw224_nextBlock, %function
+bmw224_nextBlock:
+	@ args = 0, pretend = 0, frame = 8
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #8
+	str	r0, [fp, #-8]
+	str	r1, [fp, #-12]
+	ldr	r0, [fp, #-8]
+	ldr	r1, [fp, #-12]
+	bl	bmw_small_nextBlock
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw224_nextBlock, .-bmw224_nextBlock
+	.align	2
+	.global	bmw256_nextBlock
+	.type	bmw256_nextBlock, %function
+bmw256_nextBlock:
+	@ args = 0, pretend = 0, frame = 8
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #8
+	str	r0, [fp, #-8]
+	str	r1, [fp, #-12]
+	ldr	r0, [fp, #-8]
+	ldr	r1, [fp, #-12]
+	bl	bmw_small_nextBlock
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw256_nextBlock, .-bmw256_nextBlock
+	.align	2
+	.global	bmw224_lastBlock
+	.type	bmw224_lastBlock, %function
+bmw224_lastBlock:
+	@ args = 0, pretend = 0, frame = 16
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #16
+	str	r0, [fp, #-8]
+	str	r1, [fp, #-12]
+	mov	r3, r2
+	strh	r3, [fp, #-14]	@ movhi
+	ldrh	r3, [fp, #-14]
+	ldr	r0, [fp, #-8]
+	ldr	r1, [fp, #-12]
+	mov	r2, r3
+	bl	bmw_small_lastBlock
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw224_lastBlock, .-bmw224_lastBlock
+	.align	2
+	.global	bmw256_lastBlock
+	.type	bmw256_lastBlock, %function
+bmw256_lastBlock:
+	@ args = 0, pretend = 0, frame = 16
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #16
+	str	r0, [fp, #-8]
+	str	r1, [fp, #-12]
+	mov	r3, r2
+	strh	r3, [fp, #-14]	@ movhi
+	ldrh	r3, [fp, #-14]
+	ldr	r0, [fp, #-8]
+	ldr	r1, [fp, #-12]
+	mov	r2, r3
+	bl	bmw_small_lastBlock
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw256_lastBlock, .-bmw256_lastBlock
+	.align	2
+	.global	bmw224_ctx2hash
+	.type	bmw224_ctx2hash, %function
+bmw224_ctx2hash:
+	@ args = 0, pretend = 0, frame = 8
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #8
+	str	r0, [fp, #-8]
+	str	r1, [fp, #-12]
+	ldr	r3, [fp, #-12]
+	add	r3, r3, #36
+	ldr	r0, [fp, #-8]
+	mov	r1, r3
+	mov	r2, #28
+	bl	memcpy
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw224_ctx2hash, .-bmw224_ctx2hash
+	.align	2
+	.global	bmw256_ctx2hash
+	.type	bmw256_ctx2hash, %function
+bmw256_ctx2hash:
+	@ args = 0, pretend = 0, frame = 8
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #8
+	str	r0, [fp, #-8]
+	str	r1, [fp, #-12]
+	ldr	r3, [fp, #-12]
+	add	r3, r3, #32
+	ldr	r0, [fp, #-8]
+	mov	r1, r3
+	mov	r2, #32
+	bl	memcpy
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw256_ctx2hash, .-bmw256_ctx2hash
+	.align	2
+	.global	bmw224
+	.type	bmw224, %function
+bmw224:
+	@ args = 0, pretend = 0, frame = 88
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #88
+	str	r0, [fp, #-80]
+	str	r1, [fp, #-84]
+	str	r2, [fp, #-88]
+	sub	r3, fp, #72
+	mov	r0, r3
+	bl	bmw224_init
+	b	.L120
+.L121:
+	sub	r3, fp, #72
+	mov	r0, r3
+	ldr	r1, [fp, #-84]
+	bl	bmw_small_nextBlock
+	ldr	r3, [fp, #-88]
+	sub	r3, r3, #512
+	str	r3, [fp, #-88]
+	ldr	r3, [fp, #-84]
+	add	r3, r3, #64
+	str	r3, [fp, #-84]
+.L120:
+	ldr	r2, [fp, #-88]
+	movw	r3, #511
+	cmp	r2, r3
+	bhi	.L121
+	ldr	r3, [fp, #-88]
+	uxth	r3, r3
+	sub	r2, fp, #72
+	mov	r0, r2
+	ldr	r1, [fp, #-84]
+	mov	r2, r3
+	bl	bmw_small_lastBlock
+	sub	r3, fp, #72
+	ldr	r0, [fp, #-80]
+	mov	r1, r3
+	bl	bmw224_ctx2hash
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw224, .-bmw224
+	.align	2
+	.global	bmw256
+	.type	bmw256, %function
+bmw256:
+	@ args = 0, pretend = 0, frame = 88
+	@ frame_needed = 1, uses_anonymous_args = 0
+	stmfd	sp!, {fp, lr}
+	add	fp, sp, #4
+	sub	sp, sp, #88
+	str	r0, [fp, #-80]
+	str	r1, [fp, #-84]
+	str	r2, [fp, #-88]
+	sub	r3, fp, #72
+	mov	r0, r3
+	bl	bmw256_init
+	b	.L123
+.L124:
+	sub	r3, fp, #72
+	mov	r0, r3
+	ldr	r1, [fp, #-84]
+	bl	bmw_small_nextBlock
+	ldr	r3, [fp, #-88]
+	sub	r3, r3, #512
+	str	r3, [fp, #-88]
+	ldr	r3, [fp, #-84]
+	add	r3, r3, #64
+	str	r3, [fp, #-84]
+.L123:
+	ldr	r2, [fp, #-88]
+	movw	r3, #511
+	cmp	r2, r3
+	bhi	.L124
+	ldr	r3, [fp, #-88]
+	uxth	r3, r3
+	sub	r2, fp, #72
+	mov	r0, r2
+	ldr	r1, [fp, #-84]
+	mov	r2, r3
+	bl	bmw_small_lastBlock
+	sub	r3, fp, #72
+	ldr	r0, [fp, #-80]
+	mov	r1, r3
+	bl	bmw256_ctx2hash
+	sub	sp, fp, #4
+	ldmfd	sp!, {fp, pc}
+	.size	bmw256, .-bmw256
+	.ident	"GCC: (GNU) 4.5.1"
diff --git a/bmw/f0_small_autogen.i b/bmw/f0_small_autogen.i
new file mode 100644
index 0000000..bc48783
--- /dev/null
+++ b/bmw/f0_small_autogen.i
@@ -0,0 +1,207 @@
+/*=== W[ 0] ===*/
+  ldr r14, T05_ADDR
+  ldr r12, T07_ADDR
+  ldr r11, T10_ADDR
+  ldr r10, T13_ADDR
+  ldr r9, T14_ADDR
+  sub r3, r9, r12
+/*(-- should do +10, +13, +1tr, +5 --)*/
+  add r5, r11, r10
+  add r5, r3
+  add r5, r14
+  S32_0 r8 r5
+  ldr r5, [r1, #1*4]
+  add r8, r5
+  str r8, [r0, #0*4]
+/*=== W[ 3] ===*/
+  ldr r14, T00_ADDR
+  ldr r9, T01_ADDR
+  ldr r8, T08_ADDR
+  ldr r7, T10_ADDR
+  ldr r6, T13_ADDR
+  add r2, r9, r11
+/*(-- should do +0, +13, +8, -2tr --)*/
+  add r5, r14, r10
+  add r5, r8
+  sub r5, r2
+  S32_3 r9 r5
+  ldr r5, [r1, #4*4]
+  add r9, r5
+  str r9, [r0, #3*4]
+/*=== W[ 6] ===*/
+  ldr r12, T00_ADDR
+  ldr r11, T03_ADDR
+  ldr r9, T04_ADDR
+  ldr r8, T11_ADDR
+  ldr r7, T13_ADDR
+/*(-- should do +13, +4, -0, -11, -3 --)*/
+  add r5, r10, r9
+  sub r5, r14
+  sub r5, r8
+  sub r5, r11
+  S32_1 r8 r5
+  ldr r5, [r1, #7*4]
+  add r8, r5
+  str r8, [r0, #6*4]
+/*=== W[ 9] ===*/
+  ldr r10, T00_ADDR
+  ldr r9, T03_ADDR
+  ldr r8, T06_ADDR
+  sub r4, r8, r11
+/*(-- should do +0, +0tr, +1tr --)*/
+  add r5, r14, r4
+  add r5, r3
+  S32_4 r5
+  ldr r11, [r1, #10*4]
+  add r5, r11
+  str r5, [r0, #9*4]
+/*=== W[12] ===*/
+  ldr r11, T09_ADDR
+/*(-- should do +2tr, -0tr, -9 --)*/
+  sub r5, r2, r4
+  sub r5, r11
+  S32_2 r7 r5
+  ldr r5, [r1, #13*4]
+  add r7, r5
+  str r7, [r0, #12*4]
+/*=== W[15] ===*/
+  ldr r14, T04_ADDR
+  ldr r12, T06_ADDR
+  ldr r10, T09_ADDR
+  ldr r9, T12_ADDR
+  ldr r7, T13_ADDR
+  sub r4, r9, r11
+  sub r3, r7, r12
+/*(-- should do +0tr, +1tr, -4 --)*/
+  add r5, r4, r3
+  sub r5, r14
+  S32_0 r7 r5
+  ldr r5, [r1, #0*4]
+  add r7, r5
+  str r7, [r0, #15*4]
+/*=== W[ 2] ===*/
+  ldr r14, T00_ADDR
+  ldr r7, T07_ADDR
+  ldr r6, T15_ADDR
+/*(-- should do +0, +15, +7, -0tr --)*/
+  add r5, r14, r6
+  add r5, r7
+  sub r5, r4
+  S32_2 r7 r5
+  ldr r5, [r1, #3*4]
+  add r7, r5
+  str r7, [r0, #2*4]
+/*=== W[ 5] ===*/
+  ldr r14, T02_ADDR
+  ldr r12, T03_ADDR
+  ldr r11, T10_ADDR
+  ldr r8, T12_ADDR
+  ldr r7, T15_ADDR
+  sub r4, r7, r14
+  sub r2, r12, r9
+/*(-- should do +0tr, +10, +2tr --)*/
+  add r5, r4, r11
+  add r5, r2
+  S32_0 r12 r5
+  ldr r5, [r1, #6*4]
+  add r12, r5
+  str r12, [r0, #5*4]
+/*=== W[ 8] ===*/
+  ldr r12, T05_ADDR
+/*(-- should do +1tr, -0tr, -5 --)*/
+  sub r5, r3, r4
+  sub r5, r12
+  S32_3 r11 r5
+  ldr r5, [r1, #9*4]
+  add r11, r5
+  str r11, [r0, #8*4]
+/*=== W[11] ===*/
+  ldr r11, T00_ADDR
+  ldr r9, T02_ADDR
+  ldr r8, T05_ADDR
+  ldr r7, T08_ADDR
+  ldr r6, T09_ADDR
+  sub r4, r7, r12
+/*(-- should do +0tr, +9, -0, -2 --)*/
+  add r5, r4, r10
+  sub r5, r11
+  sub r5, r14
+  S32_1 r11 r5
+  ldr r5, [r1, #12*4]
+  add r11, r5
+  str r11, [r0, #11*4]
+/*=== W[14] ===*/
+  ldr r11, T11_ADDR
+/*(-- should do +0tr, +2tr, -11 --)*/
+  add r5, r4, r2
+  sub r5, r11
+  S32_4 r5
+  ldr r7, [r1, #15*4]
+  add r5, r7
+  str r5, [r0, #14*4]
+/*=== W[ 1] ===*/
+  ldr r14, T06_ADDR
+  ldr r12, T08_ADDR
+  ldr r10, T11_ADDR
+  ldr r8, T14_ADDR
+  ldr r7, T15_ADDR
+  add r4, r11, r8
+  add r3, r12, r7
+/*(-- should do +0tr, +6, -1tr --)*/
+  add r5, r4, r14
+  sub r5, r3
+  S32_1 r14 r5
+  ldr r5, [r1, #2*4]
+  add r14, r5
+  str r14, [r0, #1*4]
+/*=== W[ 4] ===*/
+  ldr r14, T01_ADDR
+  ldr r12, T02_ADDR
+  ldr r7, T09_ADDR
+/*(-- should do +1, +2, +9, -0tr --)*/
+  add r5, r14, r12
+  add r5, r7
+  sub r5, r4
+  S32_4 r5
+  ldr r8, [r1, #5*4]
+  add r5, r8
+  str r5, [r0, #4*4]
+/*=== W[ 7] ===*/
+  ldr r12, T01_ADDR
+  ldr r11, T04_ADDR
+  ldr r8, T05_ADDR
+  ldr r7, T12_ADDR
+  ldr r6, T14_ADDR
+/*(-- should do +1, -12, -14, -4, -5 --)*/
+  sub r5, r14, r7
+  sub r5, r6
+  sub r5, r11
+  sub r5, r8
+  S32_2 r14 r5
+  ldr r5, [r1, #8*4]
+  add r14, r5
+  str r14, [r0, #7*4]
+/*=== W[10] ===*/
+  ldr r14, T01_ADDR
+  ldr r8, T04_ADDR
+  ldr r7, T07_ADDR
+  add r4, r11, r7
+/*(-- should do +1tr, -0tr, -1 --)*/
+  sub r5, r3, r4
+  sub r5, r14
+  S32_0 r14 r5
+  ldr r5, [r1, #11*4]
+  add r14, r5
+  str r14, [r0, #10*4]
+/*=== W[13] ===*/
+  ldr r14, T02_ADDR
+  ldr r12, T10_ADDR
+  ldr r11, T11_ADDR
+/*(-- should do +0tr, +10, +11, +2 --)*/
+  add r5, r4, r12
+  add r5, r11
+  add r5, r14
+  S32_3 r14 r5
+  ldr r5, [r1, #14*4]
+  add r14, r5
+  str r14, [r0, #13*4]
diff --git a/bmw/f0_small_autogen_mix.i b/bmw/f0_small_autogen_mix.i
new file mode 100644
index 0000000..9c30107
--- /dev/null
+++ b/bmw/f0_small_autogen_mix.i
@@ -0,0 +1,227 @@
+  sub SP, #16*4
+/*=== W[ 0] ===*/
+  ldr r14, [r1, #5*4]
+  ldr r3, [r2, #5*4]
+  eor r14, r3
+  str r14, [SP, #5*4]
+  ldr r12, [r1, #7*4]
+  ldr r3, [r2, #7*4]
+  eor r12, r3
+  str r12, [SP, #7*4]
+  ldr r11, [r1, #10*4]
+  ldr r3, [r2, #10*4]
+  eor r11, r3
+  str r11, [SP, #10*4]
+  ldr r10, [r1, #13*4]
+  ldr r3, [r2, #13*4]
+  eor r10, r3
+  str r10, [SP, #13*4]
+  ldr r9, [r1, #14*4]
+  ldr r3, [r2, #14*4]
+  eor r9, r3
+  str r9, [SP, #14*4]
+  sub r8, r9, r12
+/*(-- should do +10, +13, +1tr, +5 --)*/
+  add r3, r11, r10
+  add r3, r8
+  add r3, r14
+  S32_0 r7 r3
+  ldr r3, [r1, #1*4]
+  add r7, r3
+  str r7, [r0, #0*4]
+/*=== W[ 3] ===*/
+  ldr r7, [r1, #0*4]
+  ldr r3, [r2, #0*4]
+  eor r7, r3
+  str r7, [SP, #0*4]
+  ldr r6, [r1, #1*4]
+  ldr r3, [r2, #1*4]
+  eor r6, r3
+  str r6, [SP, #1*4]
+  ldr r5, [r1, #8*4]
+  ldr r3, [r2, #8*4]
+  eor r5, r3
+  str r5, [SP, #8*4]
+  add r4, r6, r11
+/*(-- should do +0, +13, +8, -2tr --)*/
+  add r3, r7, r10
+  add r3, r5
+  sub r3, r4
+  S32_3 r6 r3
+  ldr r3, [r1, #4*4]
+  add r6, r3
+  str r6, [r0, #3*4]
+/*=== W[ 6] ===*/
+  ldr r9, [r1, #3*4]
+  ldr r3, [r2, #3*4]
+  eor r9, r3
+  str r9, [SP, #3*4]
+  ldr r6, [r1, #4*4]
+  ldr r3, [r2, #4*4]
+  eor r6, r3
+  str r6, [SP, #4*4]
+  ldr r5, [r1, #11*4]
+  ldr r3, [r2, #11*4]
+  eor r5, r3
+  str r5, [SP, #11*4]
+/*(-- should do +13, +4, -0, -11, -3 --)*/
+  add r3, r10, r6
+  sub r3, r7
+  sub r3, r5
+  sub r3, r9
+  S32_1 r5 r3
+  ldr r3, [r1, #7*4]
+  add r5, r3
+  str r5, [r0, #6*4]
+/*=== W[ 9] ===*/
+  ldr r5, [r1, #6*4]
+  ldr r3, [r2, #6*4]
+  eor r5, r3
+  str r5, [SP, #6*4]
+  sub r14, r5, r9
+/*(-- should do +0, +0tr, +1tr --)*/
+  add r3, r7, r14
+  add r3, r8
+  S32_4 r3
+  ldr r8, [r1, #10*4]
+  add r3, r8
+  str r3, [r0, #9*4]
+/*=== W[12] ===*/
+  ldr r8, [r1, #9*4]
+  ldr r3, [r2, #9*4]
+  eor r8, r3
+  str r8, [SP, #9*4]
+/*(-- should do +2tr, -0tr, -9 --)*/
+  sub r3, r4, r14
+  sub r3, r8
+  S32_2 r14 r3
+  ldr r3, [r1, #13*4]
+  add r14, r3
+  str r14, [r0, #12*4]
+/*=== W[15] ===*/
+  ldr r14, [r1, #12*4]
+  ldr r3, [r2, #12*4]
+  eor r14, r3
+  str r14, [SP, #12*4]
+  sub r4, r14, r8
+  sub r11, r10, r5
+/*(-- should do +0tr, +1tr, -4 --)*/
+  add r3, r4, r11
+  sub r3, r6
+  S32_0 r10 r3
+  ldr r3, [r1, #0*4]
+  add r10, r3
+  str r10, [r0, #15*4]
+/*=== W[ 2] ===*/
+  ldr r10, [r1, #15*4]
+  ldr r3, [r2, #15*4]
+  eor r10, r3
+  str r10, [SP, #15*4]
+/*(-- should do +0, +15, +7, -0tr --)*/
+  add r3, r7, r10
+  add r3, r12
+  sub r3, r4
+  S32_2 r4 r3
+  ldr r3, [r1, #3*4]
+  add r4, r3
+  str r4, [r0, #2*4]
+/*=== W[ 5] ===*/
+  ldr r12, [r1, #2*4]
+  ldr r3, [r2, #2*4]
+  eor r12, r3
+  str r12, [SP, #2*4]
+  ldr r4, [SP, #10*4]
+  sub r6, r10, r12
+  sub r5, r9, r14
+/*(-- should do +0tr, +10, +2tr --)*/
+  add r3, r6, r4
+  add r3, r5
+  S32_0 r9 r3
+  ldr r3, [r1, #6*4]
+  add r9, r3
+  str r9, [r0, #5*4]
+/*=== W[ 8] ===*/
+  ldr r9, [SP, #5*4]
+/*(-- should do +1tr, -0tr, -5 --)*/
+  sub r3, r11, r6
+  sub r3, r9
+  S32_3 r11 r3
+  ldr r3, [r1, #9*4]
+  add r11, r3
+  str r11, [r0, #8*4]
+/*=== W[11] ===*/
+  ldr r11, [SP, #8*4]
+  sub r6, r11, r9
+/*(-- should do +0tr, +9, -0, -2 --)*/
+  add r3, r6, r8
+  sub r3, r7
+  sub r3, r12
+  S32_1 r7 r3
+  ldr r3, [r1, #12*4]
+  add r7, r3
+  str r7, [r0, #11*4]
+/*=== W[14] ===*/
+  ldr r7, [SP, #11*4]
+/*(-- should do +0tr, +2tr, -11 --)*/
+  add r3, r6, r5
+  sub r3, r7
+  S32_4 r3
+  ldr r6, [r1, #15*4]
+  add r3, r6
+  str r3, [r0, #14*4]
+/*=== W[ 1] ===*/
+  ldr r6, [SP, #6*4]
+  ldr r5, [SP, #14*4]
+  add r4, r7, r5
+  add r14, r11, r10
+/*(-- should do +0tr, +6, -1tr --)*/
+  add r3, r4, r6
+  sub r3, r14
+  S32_1 r11 r3
+  ldr r3, [r1, #2*4]
+  add r11, r3
+  str r11, [r0, #1*4]
+/*=== W[ 4] ===*/
+  ldr r11, [SP, #1*4]
+/*(-- should do +1, +2, +9, -0tr --)*/
+  add r3, r11, r12
+  add r3, r8
+  sub r3, r4
+  S32_4 r3
+  ldr r4, [r1, #5*4]
+  add r3, r4
+  str r3, [r0, #4*4]
+/*=== W[ 7] ===*/
+  ldr r10, [SP, #4*4]
+  ldr r4, [SP, #12*4]
+/*(-- should do +1, -12, -14, -4, -5 --)*/
+  sub r3, r11, r4
+  sub r3, r5
+  sub r3, r10
+  sub r3, r9
+  S32_2 r11 r3
+  ldr r3, [r1, #8*4]
+  add r11, r3
+  str r11, [r0, #7*4]
+/*=== W[10] ===*/
+  ldr r11, [SP, #1*4]
+  ldr r9, [SP, #7*4]
+  add r8, r10, r9
+/*(-- should do +1tr, -0tr, -1 --)*/
+  sub r3, r14, r8
+  sub r3, r11
+  S32_0 r14 r3
+  ldr r3, [r1, #11*4]
+  add r14, r3
+  str r14, [r0, #10*4]
+/*=== W[13] ===*/
+  ldr r14, [SP, #10*4]
+/*(-- should do +0tr, +10, +11, +2 --)*/
+  add r3, r8, r14
+  add r3, r7
+  add r3, r12
+  S32_3 r8 r3
+  ldr r3, [r1, #14*4]
+  add r8, r3
+  str r8, [r0, #13*4]
+  add SP, #16*4
diff --git a/bmw/f1_autogen_neon_small.i b/bmw/f1_autogen_neon_small.i
new file mode 100644
index 0000000..b309e7e
--- /dev/null
+++ b/bmw/f1_autogen_neon_small.i
@@ -0,0 +1,330 @@
+/* BEGIN of automatic generated code */
+/*
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+static inline
+void bmw_small_f1(uint32_t* q, const uint32_t* m, const uint32_t* h){ 
+  uint32_t even, odd;
+  uint32x4_t qq16, qq20, qq24, qq28;
+  uint32x4_t qm0, qm1, qm2;
+  uint32x4_t qk={0x55555550UL, 0x5aaaaaa5UL, 0x5ffffffaUL, 0x6555554fUL};
+  uint32x4_t qkadd={0x15555554UL, 0x15555554UL, 0x15555554UL, 0x15555554UL};
+  uint32x2_t dtmp0;
+  uint32x4x2_t q2tmp0, q2tmp1;   
+
+  /* addElement for q16 .. q19 */
+  qm0 = *((uint32x4_t*)&(m[ 0]));
+  qm1 = *((uint32x4_t*)&(m[ 3]));
+  qm2 = *((uint32x4_t*)&(m[10]));
+  qm0 = veorq_u32(vshlq_u32(qm0,(int32x4_t){ 1,  2,  3,  4}),vshlq_u32(qm0,(int32x4_t){-31, -30, -29, -28}));
+  qm1 = veorq_u32(vshlq_u32(qm1,(int32x4_t){ 4,  5,  6,  7}),vshlq_u32(qm1,(int32x4_t){-28, -27, -26, -25}));
+  qm2 = veorq_u32(vshlq_u32(qm2,(int32x4_t){11, 12, 13, 14}),vshlq_u32(qm2,(int32x4_t){-21, -20, -19, -18}));
+  qq16 = veorq_u32(vaddq_u32(vaddq_u32(qm0, qm1),vsubq_u32(qk, qm2)), *((uint32x4_t*)&(h[ 7])));
+  qk = vaddq_u32(qk, qkadd);
+
+  /* addElement for q20 .. q23 */
+  qm0 = *((uint32x4_t*)&(m[ 4]));
+  qm1 = *((uint32x4_t*)&(m[ 7]));
+  qm2 = *((uint32x4_t*)&(m[14]));
+  qm0 = veorq_u32(vshlq_u32(qm0,(int32x4_t){ 5,  6,  7,  8}),vshlq_u32(qm0,(int32x4_t){-27, -26, -25, -24}));
+  qm1 = veorq_u32(vshlq_u32(qm1,(int32x4_t){ 8,  9, 10, 11}),vshlq_u32(qm1,(int32x4_t){-24, -23, -22, -21}));
+  qm2 = veorq_u32(vshlq_u32(qm2,(int32x4_t){15, 16,  1,  2}),vshlq_u32(qm2,(int32x4_t){-17, -16, -31, -30}));
+  qq20 = veorq_u32(vaddq_u32(vaddq_u32(qm0, qm1),vsubq_u32(qk, qm2)), *((uint32x4_t*)&(h[11])));
+  qk = vaddq_u32(qk, qkadd);
+
+  /* addElement for q24 .. q27 */
+  qm0 = *((uint32x4_t*)&(m[ 8]));
+  qm1 = *((uint32x4_t*)&(m[11]));
+  qm2 = *((uint32x4_t*)&(m[18]));
+  qm0 = veorq_u32(vshlq_u32(qm0,(int32x4_t){ 9, 10, 11, 12}),vshlq_u32(qm0,(int32x4_t){-23, -22, -21, -20}));
+  qm1 = veorq_u32(vshlq_u32(qm1,(int32x4_t){12, 13, 14, 15}),vshlq_u32(qm1,(int32x4_t){-20, -19, -18, -17}));
+  qm2 = veorq_u32(vshlq_u32(qm2,(int32x4_t){ 3,  4,  5,  6}),vshlq_u32(qm2,(int32x4_t){-29, -28, -27, -26}));
+  qq24 = veorq_u32(vaddq_u32(vaddq_u32(qm0, qm1),vsubq_u32(qk, qm2)), *((uint32x4_t*)&(h[15])));
+  qk = vaddq_u32(qk, qkadd);
+
+  /* addElement for q28 .. q31 */
+  qm0 = *((uint32x4_t*)&(m[12]));
+  qm1 = *((uint32x4_t*)&(m[15]));
+  qm2 = *((uint32x4_t*)&(m[22]));
+  qm0 = veorq_u32(vshlq_u32(qm0,(int32x4_t){13, 14, 15, 16}),vshlq_u32(qm0,(int32x4_t){-19, -18, -17, -16}));
+  qm1 = veorq_u32(vshlq_u32(qm1,(int32x4_t){16,  1,  2,  3}),vshlq_u32(qm1,(int32x4_t){-16, -31, -30, -29}));
+  qm2 = veorq_u32(vshlq_u32(qm2,(int32x4_t){ 7,  8,  9, 10}),vshlq_u32(qm2,(int32x4_t){-25, -24, -23, -22}));
+  qq28 = veorq_u32(vaddq_u32(vaddq_u32(qm0, qm1),vsubq_u32(qk, qm2)), *((uint32x4_t*)&(h[ 3])));
+  qk = vaddq_u32(qk, qkadd);
+
+  /* expand1( 0) */
+  qm0 = *((uint32x4_t*)&(q[ 0]));
+  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}), 
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm0 = *((uint32x4_t*)&(q[ 4]));
+  qm2 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm2 = vaddq_u32(qm2, qm1);
+  qm0 = *((uint32x4_t*)&(q[ 8]));
+  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm2 = vaddq_u32(qm2, qm1);
+  qm0 = *((uint32x4_t*)&(q[12]));
+  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm2 = vaddq_u32(qm2, qm1);
+  dtmp0 = vadd_u32(vget_high_u32(qm2), vget_low_u32(qm2));
+  q[16] = vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1) + vgetq_lane_u32(qq16,  0);
+
+  /* expand1( 1) */
+  qm0 = *((uint32x4_t*)&(q[ 1]));
+  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}), 
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm0 = *((uint32x4_t*)&(q[ 5]));
+  qm2 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm2 = vaddq_u32(qm2, qm1);
+  qm0 = *((uint32x4_t*)&(q[ 9]));
+  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm2 = vaddq_u32(qm2, qm1);
+  qm0 = *((uint32x4_t*)&(q[13]));
+  qm1 = veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){ -1, -2, -2, -1}),
+                            vshlq_u32(qm0,(int32x4_t){  2,  1,  2,  3})),
+                  veorq_u32(veorq_u32(vshlq_u32(qm0,(int32x4_t){  8, 12, 15,  4}),
+                                      vshlq_u32(qm0,(int32x4_t){-24,-20,-17,-28})),
+                            veorq_u32(vshlq_u32(qm0,(int32x4_t){ 23, 25, 29, 19}),
+                                      vshlq_u32(qm0,(int32x4_t){ -9, -7, -3,-13}))));
+  qm2 = vaddq_u32(qm2, qm1);
+  dtmp0 = vadd_u32(vget_high_u32(qm2), vget_low_u32(qm2));
+  q[17] = vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1) + vgetq_lane_u32(qq16,  1);
+
+  /* expand2( 2) */
+  q2tmp0 = vld2q_u32(&q[ 2]);
+  q2tmp1 = vld2q_u32(&q[10]);
+  q2tmp1.val[0] = vsetq_lane_u32(0, q2tmp1.val[0], 3);
+  q2tmp0.val[0] = vaddq_u32(q2tmp0.val[0], q2tmp1.val[0]);
+  dtmp0 = vadd_u32(vget_high_u32(q2tmp0.val[0]), vget_low_u32(q2tmp0.val[0]));
+  even = vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+  q[18] = even + ((q[16]>>1)|q[16]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[18] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 3) */
+  q2tmp0 = vld2q_u32(&q[ 3]);
+  q2tmp1 = vld2q_u32(&q[11]);
+  q2tmp1.val[0] = vsetq_lane_u32(0, q2tmp1.val[0], 3);
+  q2tmp0.val[0] = vaddq_u32(q2tmp0.val[0], q2tmp1.val[0]);
+  dtmp0 = vadd_u32(vget_high_u32(q2tmp0.val[0]), vget_low_u32(q2tmp0.val[0]));
+  odd  = vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+  q[19] = odd  + ((q[17]>>1)|q[17]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[19] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 4) */
+  q2tmp0 = vld2q_u32(&q[ 4]);
+  q2tmp1 = vld2q_u32(&q[12]);
+  even += q[16] - q[ 2];
+  q[20] = even + ((q[18]>>1)|q[18]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[20] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 5) */
+  q2tmp0 = vld2q_u32(&q[ 5]);
+  q2tmp1 = vld2q_u32(&q[13]);
+  odd  += q[17] - q[ 3];
+  q[21] = odd  + ((q[19]>>1)|q[19]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[21] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 6) */
+  q2tmp0 = vld2q_u32(&q[ 6]);
+  q2tmp1 = vld2q_u32(&q[14]);
+  even += q[18] - q[ 4];
+  q[22] = even + ((q[20]>>1)|q[20]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[22] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 7) */
+  q2tmp0 = vld2q_u32(&q[ 7]);
+  q2tmp1 = vld2q_u32(&q[15]);
+  odd  += q[19] - q[ 5];
+  q[23] = odd  + ((q[21]>>1)|q[21]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[23] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 8) */
+  q2tmp0 = vld2q_u32(&q[ 8]);
+  q2tmp1 = vld2q_u32(&q[16]);
+  even += q[20] - q[ 6];
+  q[24] = even + ((q[22]>>1)|q[22]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[24] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2( 9) */
+  q2tmp0 = vld2q_u32(&q[ 9]);
+  q2tmp1 = vld2q_u32(&q[17]);
+  odd  += q[21] - q[ 7];
+  q[25] = odd  + ((q[23]>>1)|q[23]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[25] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2(10) */
+  q2tmp0 = vld2q_u32(&q[10]);
+  q2tmp1 = vld2q_u32(&q[18]);
+  even += q[22] - q[ 8];
+  q[26] = even + ((q[24]>>1)|q[24]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[26] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2(11) */
+  q2tmp0 = vld2q_u32(&q[11]);
+  q2tmp1 = vld2q_u32(&q[19]);
+  odd  += q[23] - q[ 9];
+  q[27] = odd  + ((q[25]>>1)|q[25]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[27] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2(12) */
+  q2tmp0 = vld2q_u32(&q[12]);
+  q2tmp1 = vld2q_u32(&q[20]);
+  even += q[24] - q[10];
+  q[28] = even + ((q[26]>>1)|q[26]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[28] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2(13) */
+  q2tmp0 = vld2q_u32(&q[13]);
+  q2tmp1 = vld2q_u32(&q[21]);
+  odd  += q[25] - q[11];
+  q[29] = odd  + ((q[27]>>1)|q[27]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[29] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2(14) */
+  q2tmp0 = vld2q_u32(&q[14]);
+  q2tmp1 = vld2q_u32(&q[22]);
+  even += q[26] - q[12];
+  q[30] = even + ((q[28]>>1)|q[28]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[30] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+
+  /* expand2(15) */
+  q2tmp0 = vld2q_u32(&q[15]);
+  q2tmp1 = vld2q_u32(&q[23]);
+  odd  += q[27] - q[13];
+  q[31] = odd  + ((q[29]>>1)|q[29]);
+  qm0 = veorq_u32(vshlq_u32(q2tmp0.val[1],(int32x4_t){  3,  7, 13, 16}),
+                  vshlq_u32(q2tmp0.val[1],(int32x4_t){-29,-25,-19,-16}));
+  qm1 = veorq_u32(vshlq_u32(q2tmp1.val[1],(int32x4_t){ 19, 23, 27,  0}),
+                  vshlq_u32(q2tmp1.val[1],(int32x4_t){-13, -9, -5, -2}));
+  qm1 = vaddq_u32(qm1, qm0);
+  dtmp0 = vadd_u32(vget_high_u32(qm1), vget_low_u32(qm1));
+  q[31] += vget_lane_u32(dtmp0, 0) + vget_lane_u32(dtmp0, 1);
+}
+
+/* END of automatic generated code */
+
diff --git a/bmw/gen_f0_arm.rb b/bmw/gen_f0_arm.rb
new file mode 100644
index 0000000..c1e2797
--- /dev/null
+++ b/bmw/gen_f0_arm.rb
@@ -0,0 +1,59 @@
+# gen_f0_arm.rb 
+=begin
+    This file is part of the ARM-Crypto-Lib.
+    Copyright (C) 2006-2010  Daniel Otte (daniel.otte@rub.de)
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+=end
+=begin
+#define S32_1(x) ( (SHR32((x),   1)) ^ \
+                 (SHL32((x),   2)) ^ \
+                 (ROTL32((x),  8)) ^ \
+                 (ROTR32((x),  9)) )
+
+#define S32_2(x) ( (SHR32((x),   2)) ^ \
+                 (SHL32((x),   1)) ^ \
+                 (ROTL32((x), 12)) ^ \
+                 (ROTR32((x),  7)) )
+
+#define S32_3(x) ( (SHR32((x),   2)) ^ \
+                 (SHL32((x),   2)) ^ \
+                 (ROTL32((x), 15)) ^ \
+                 (ROTR32((x),  3)) )
+
+#define S32_4(x) ( (SHR32((x),   1)) ^ (x))
+
+#define S32_5(x) ( (SHR32((x),   2)) ^ (x))
+
+=end
+$s32_0_lut = [ 1,  3,  4, 13]
+$s32_1_lut = [ 1,  2,  8,  9]
+$s32_2_lut = [ 2,  1, 12,  7]
+$s32_3_lut = [ 2,  2, 15,  3]
+
+$s32_lut = [$s32_0_lut, $s32_1_lut, $s32_2_lut, $s32_3_lut]
+
+def s32_0(fout, select, reg0, reg1)
+  if select<=3
+    fout.puts("\tmov %s, %s", reg1, reg0)
+    fout.puts("\tlsrs %s, %s, #%d", reg0, reg0, $s32_lut[select][0])
+    fout.puts("\teor %s, %s, %s, lsl #%d", reg0, reg0, reg1, $s32_lut[select][1])
+    fout.puts("\teor %s, %s, %s, ror #%d", reg0, reg0, reg1, 32-$s32_lut[select][2])
+    fout.puts("\teor %s, %s, %s, ror #%d", reg0, reg0, reg1, $s32_lut[select][3])
+  else
+    fout.puts("\teor %s, %s, %s, ror #%d", reg0, reg0, reg0, 1) if select==4
+    fout.puts("\teor %s, %s, %s, ror #%d", reg0, reg0, reg0, 2) if select==5
+  end
+end
+
-- 
2.39.5