1 //*****************************************************************************
\r
3 // hw_uart.h - Macros and defines used when accessing the UART hardware.
\r
5 // Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
\r
6 // Software License Agreement
\r
8 // Texas Instruments (TI) is supplying this software for use solely and
\r
9 // exclusively on TI's microcontroller products. The software is owned by
\r
10 // TI and/or its suppliers, and is protected under applicable copyright
\r
11 // laws. You may not combine this software with "viral" open-source
\r
12 // software in order to form a larger program.
\r
14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
\r
15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
\r
16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
\r
17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
\r
18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
\r
19 // DAMAGES, FOR ANY REASON WHATSOEVER.
\r
21 // This is part of revision 5821 of the Stellaris Firmware Development Package.
\r
23 //*****************************************************************************
\r
25 #ifndef __HW_UART_H__
\r
26 #define __HW_UART_H__
\r
28 //*****************************************************************************
\r
30 // The following are defines for the UART register offsets.
\r
32 //*****************************************************************************
\r
33 #define UART_O_DR 0x00000000 // UART Data
\r
34 #define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
\r
35 #define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
\r
36 #define UART_O_FR 0x00000018 // UART Flag
\r
37 #define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
\r
38 #define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
\r
39 #define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
\r
41 #define UART_O_LCRH 0x0000002C // UART Line Control
\r
42 #define UART_O_CTL 0x00000030 // UART Control
\r
43 #define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
\r
44 #define UART_O_IM 0x00000038 // UART Interrupt Mask
\r
45 #define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
\r
46 #define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
\r
47 #define UART_O_ICR 0x00000044 // UART Interrupt Clear
\r
48 #define UART_O_DMACTL 0x00000048 // UART DMA Control
\r
49 #define UART_O_LCTL 0x00000090 // UART LIN Control
\r
50 #define UART_O_LSS 0x00000094 // UART LIN Snap Shot
\r
51 #define UART_O_LTIM 0x00000098 // UART LIN Timer
\r
53 //*****************************************************************************
\r
55 // The following are defines for the bit fields in the UART_O_DR register.
\r
57 //*****************************************************************************
\r
58 #define UART_DR_OE 0x00000800 // UART Overrun Error
\r
59 #define UART_DR_BE 0x00000400 // UART Break Error
\r
60 #define UART_DR_PE 0x00000200 // UART Parity Error
\r
61 #define UART_DR_FE 0x00000100 // UART Framing Error
\r
62 #define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
\r
63 #define UART_DR_DATA_S 0
\r
65 //*****************************************************************************
\r
67 // The following are defines for the bit fields in the UART_O_RSR register.
\r
69 //*****************************************************************************
\r
70 #define UART_RSR_OE 0x00000008 // UART Overrun Error
\r
71 #define UART_RSR_BE 0x00000004 // UART Break Error
\r
72 #define UART_RSR_PE 0x00000002 // UART Parity Error
\r
73 #define UART_RSR_FE 0x00000001 // UART Framing Error
\r
75 //*****************************************************************************
\r
77 // The following are defines for the bit fields in the UART_O_ECR register.
\r
79 //*****************************************************************************
\r
80 #define UART_ECR_DATA_M 0x000000FF // Error Clear
\r
81 #define UART_ECR_DATA_S 0
\r
83 //*****************************************************************************
\r
85 // The following are defines for the bit fields in the UART_O_FR register.
\r
87 //*****************************************************************************
\r
88 #define UART_FR_RI 0x00000100 // Ring Indicator
\r
89 #define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
\r
90 #define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
\r
91 #define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
\r
92 #define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
\r
93 #define UART_FR_BUSY 0x00000008 // UART Busy
\r
94 #define UART_FR_DCD 0x00000004 // Data Carrier Detect
\r
95 #define UART_FR_DSR 0x00000002 // Data Set Ready
\r
96 #define UART_FR_CTS 0x00000001 // Clear To Send
\r
98 //*****************************************************************************
\r
100 // The following are defines for the bit fields in the UART_O_ILPR register.
\r
102 //*****************************************************************************
\r
103 #define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
\r
104 #define UART_ILPR_ILPDVSR_S 0
\r
106 //*****************************************************************************
\r
108 // The following are defines for the bit fields in the UART_O_IBRD register.
\r
110 //*****************************************************************************
\r
111 #define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
\r
112 #define UART_IBRD_DIVINT_S 0
\r
114 //*****************************************************************************
\r
116 // The following are defines for the bit fields in the UART_O_FBRD register.
\r
118 //*****************************************************************************
\r
119 #define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
\r
120 #define UART_FBRD_DIVFRAC_S 0
\r
122 //*****************************************************************************
\r
124 // The following are defines for the bit fields in the UART_O_LCRH register.
\r
126 //*****************************************************************************
\r
127 #define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
\r
128 #define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
\r
129 #define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
\r
130 #define UART_LCRH_WLEN_6 0x00000020 // 6 bits
\r
131 #define UART_LCRH_WLEN_7 0x00000040 // 7 bits
\r
132 #define UART_LCRH_WLEN_8 0x00000060 // 8 bits
\r
133 #define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
\r
134 #define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
\r
135 #define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
\r
136 #define UART_LCRH_PEN 0x00000002 // UART Parity Enable
\r
137 #define UART_LCRH_BRK 0x00000001 // UART Send Break
\r
139 //*****************************************************************************
\r
141 // The following are defines for the bit fields in the UART_O_CTL register.
\r
143 //*****************************************************************************
\r
144 #define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
\r
145 #define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
\r
146 #define UART_CTL_RTS 0x00000800 // Request to Send
\r
147 #define UART_CTL_DTR 0x00000400 // Data Terminal Ready
\r
148 #define UART_CTL_RXE 0x00000200 // UART Receive Enable
\r
149 #define UART_CTL_TXE 0x00000100 // UART Transmit Enable
\r
150 #define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
\r
151 #define UART_CTL_LIN 0x00000040 // LIN Mode Enable
\r
152 #define UART_CTL_HSE 0x00000020 // High-Speed Enable
\r
153 #define UART_CTL_EOT 0x00000010 // End of Transmission
\r
154 #define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
\r
155 #define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
\r
156 #define UART_CTL_SIREN 0x00000002 // UART SIR Enable
\r
157 #define UART_CTL_UARTEN 0x00000001 // UART Enable
\r
159 //*****************************************************************************
\r
161 // The following are defines for the bit fields in the UART_O_IFLS register.
\r
163 //*****************************************************************************
\r
164 #define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
\r
166 #define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
\r
167 #define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
\r
168 #define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
\r
169 #define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
\r
170 #define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
\r
171 #define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
\r
173 #define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
\r
174 #define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
\r
175 #define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
\r
176 #define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
\r
177 #define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
\r
179 //*****************************************************************************
\r
181 // The following are defines for the bit fields in the UART_O_IM register.
\r
183 //*****************************************************************************
\r
184 #define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
\r
185 #define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
\r
186 #define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
\r
188 #define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
\r
190 #define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
\r
191 #define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
\r
192 #define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
\r
194 #define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
\r
196 #define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
\r
197 #define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
\r
198 #define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
\r
200 #define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
\r
202 #define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
\r
204 #define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
\r
207 //*****************************************************************************
\r
209 // The following are defines for the bit fields in the UART_O_RIS register.
\r
211 //*****************************************************************************
\r
212 #define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
\r
214 #define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
\r
216 #define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
\r
217 // Interrupt Status
\r
218 #define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
\r
220 #define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
\r
222 #define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
\r
224 #define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
\r
226 #define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
\r
227 // Interrupt Status
\r
228 #define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
\r
230 #define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
\r
232 #define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
\r
233 // Interrupt Status
\r
234 #define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
\r
235 // Raw Interrupt Status
\r
236 #define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
\r
237 // Interrupt Status
\r
238 #define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
\r
239 // Interrupt Status
\r
241 //*****************************************************************************
\r
243 // The following are defines for the bit fields in the UART_O_MIS register.
\r
245 //*****************************************************************************
\r
246 #define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
\r
248 #define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
\r
250 #define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
\r
251 // Interrupt Status
\r
252 #define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
\r
253 // Interrupt Status
\r
254 #define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
\r
255 // Interrupt Status
\r
256 #define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
\r
257 // Interrupt Status
\r
258 #define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
\r
259 // Interrupt Status
\r
260 #define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
\r
261 // Interrupt Status
\r
262 #define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
\r
264 #define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
\r
266 #define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
\r
267 // Interrupt Status
\r
268 #define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
\r
269 // Masked Interrupt Status
\r
270 #define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
\r
271 // Interrupt Status
\r
272 #define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
\r
273 // Interrupt Status
\r
275 //*****************************************************************************
\r
277 // The following are defines for the bit fields in the UART_O_ICR register.
\r
279 //*****************************************************************************
\r
280 #define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
\r
281 #define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
\r
282 #define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
\r
284 #define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
\r
285 #define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
\r
286 #define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
\r
287 #define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
\r
288 #define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
\r
289 #define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
\r
290 #define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
\r
291 #define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
\r
293 #define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
\r
295 #define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
\r
297 #define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
\r
300 //*****************************************************************************
\r
302 // The following are defines for the bit fields in the UART_O_DMACTL register.
\r
304 //*****************************************************************************
\r
305 #define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
\r
306 #define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
\r
307 #define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
\r
309 //*****************************************************************************
\r
311 // The following are defines for the bit fields in the UART_O_LCTL register.
\r
313 //*****************************************************************************
\r
314 #define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
\r
315 #define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
\r
317 #define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
\r
318 #define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
\r
319 #define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
\r
320 #define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
\r
322 //*****************************************************************************
\r
324 // The following are defines for the bit fields in the UART_O_LSS register.
\r
326 //*****************************************************************************
\r
327 #define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
\r
328 #define UART_LSS_TSS_S 0
\r
330 //*****************************************************************************
\r
332 // The following are defines for the bit fields in the UART_O_LTIM register.
\r
334 //*****************************************************************************
\r
335 #define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
\r
336 #define UART_LTIM_TIMER_S 0
\r
338 //*****************************************************************************
\r
340 // The following definitions are deprecated.
\r
342 //*****************************************************************************
\r
345 //*****************************************************************************
\r
347 // The following are deprecated defines for the UART register offsets.
\r
349 //*****************************************************************************
\r
350 #define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
\r
351 #define UART_O_PeriphID4 0x00000FD0
\r
352 #define UART_O_PeriphID5 0x00000FD4
\r
353 #define UART_O_PeriphID6 0x00000FD8
\r
354 #define UART_O_PeriphID7 0x00000FDC
\r
355 #define UART_O_PeriphID0 0x00000FE0
\r
356 #define UART_O_PeriphID1 0x00000FE4
\r
357 #define UART_O_PeriphID2 0x00000FE8
\r
358 #define UART_O_PeriphID3 0x00000FEC
\r
359 #define UART_O_PCellID0 0x00000FF0
\r
360 #define UART_O_PCellID1 0x00000FF4
\r
361 #define UART_O_PCellID2 0x00000FF8
\r
362 #define UART_O_PCellID3 0x00000FFC
\r
364 //*****************************************************************************
\r
366 // The following are deprecated defines for the bit fields in the UART_O_DR
\r
369 //*****************************************************************************
\r
370 #define UART_DR_DATA_MASK 0x000000FF // UART data
\r
372 //*****************************************************************************
\r
374 // The following are deprecated defines for the bit fields in the UART_O_IBRD
\r
377 //*****************************************************************************
\r
378 #define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
\r
380 //*****************************************************************************
\r
382 // The following are deprecated defines for the bit fields in the UART_O_FBRD
\r
385 //*****************************************************************************
\r
386 #define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
\r
388 //*****************************************************************************
\r
390 // The following are deprecated defines for the bit fields in the UART_O_LCR_H
\r
393 //*****************************************************************************
\r
394 #define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
\r
395 #define UART_LCR_H_WLEN 0x00000060 // Word length
\r
396 #define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
\r
397 #define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
\r
398 #define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
\r
399 #define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
\r
400 #define UART_LCR_H_FEN 0x00000010 // Enable FIFO
\r
401 #define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
\r
402 #define UART_LCR_H_EPS 0x00000004 // Even Parity Select
\r
403 #define UART_LCR_H_PEN 0x00000002 // Parity Enable
\r
404 #define UART_LCR_H_BRK 0x00000001 // Send Break
\r
406 //*****************************************************************************
\r
408 // The following are deprecated defines for the bit fields in the UART_O_IFLS
\r
411 //*****************************************************************************
\r
412 #define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
\r
413 #define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
\r
415 //*****************************************************************************
\r
417 // The following are deprecated defines for the bit fields in the UART_O_ICR
\r
420 //*****************************************************************************
\r
421 #define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
\r
424 //*****************************************************************************
\r
426 // The following are deprecated defines for the Reset Values for UART
\r
429 //*****************************************************************************
\r
430 #define UART_RV_CTL 0x00000300
\r
431 #define UART_RV_PCellID1 0x000000F0
\r
432 #define UART_RV_PCellID3 0x000000B1
\r
433 #define UART_RV_FR 0x00000090
\r
434 #define UART_RV_PeriphID2 0x00000018
\r
435 #define UART_RV_IFLS 0x00000012
\r
436 #define UART_RV_PeriphID0 0x00000011
\r
437 #define UART_RV_PCellID0 0x0000000D
\r
438 #define UART_RV_PCellID2 0x00000005
\r
439 #define UART_RV_PeriphID3 0x00000001
\r
440 #define UART_RV_PeriphID4 0x00000000
\r
441 #define UART_RV_LCR_H 0x00000000
\r
442 #define UART_RV_PeriphID6 0x00000000
\r
443 #define UART_RV_DR 0x00000000
\r
444 #define UART_RV_RSR 0x00000000
\r
445 #define UART_RV_ECR 0x00000000
\r
446 #define UART_RV_PeriphID5 0x00000000
\r
447 #define UART_RV_RIS 0x00000000
\r
448 #define UART_RV_FBRD 0x00000000
\r
449 #define UART_RV_IM 0x00000000
\r
450 #define UART_RV_MIS 0x00000000
\r
451 #define UART_RV_ICR 0x00000000
\r
452 #define UART_RV_PeriphID1 0x00000000
\r
453 #define UART_RV_PeriphID7 0x00000000
\r
454 #define UART_RV_IBRD 0x00000000
\r
458 #endif // __HW_UART_H__
\r