3 This file is part of the ARM-Crypto-Lib.
4 Copyright (C) 2010 Daniel Otte (daniel.otte@rub.de)
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define SET_REG(r,v) (*((volatile uint32_t*)(r))) = (v)
26 #define GET_REG(r) (*((volatile uint32_t*)(r)))
27 #define HW_REG(r) (*((volatile uint32_t*)(r)))
28 #define _BV(x) (1<<(x))
30 #define SYSCTL_BASE 0x400FE000
31 #define DID0_OFFSET 0x000
32 #define DID1_OFFSET 0x004
33 #define DC0_OFFSET 0x008
34 #define DC1_OFFSET 0x010
35 #define DC2_OFFSET 0x014
36 #define DC3_OFFSET 0x018
37 #define DC4_OFFSET 0x01C
38 #define DC5_OFFSET 0x020
39 #define DC6_OFFSET 0x024
40 #define DC7_OFFSET 0x028
41 #define DC8_OFFSET 0x02C
42 #define PBORCTL_OFFSET 0x030
43 #define SRCR0_OFFSET 0x040
44 #define SRCR1_OFFSET 0x044
45 #define SRCR2_OFFSET 0x048
46 #define RIS_OFFSET 0x050
47 #define IMC_OFFSET 0x054
48 #define MISC_OFFSET 0x058
49 #define RESC_OFFSET 0x05C
50 #define RCC_OFFSET 0x060
51 #define PLLCFG_OFFSET 0x064
52 #define GPIOHBCTL_OFFSET 0x06C
53 #define RCC2_OFFSET 0x070
54 #define MOSCCTL_OFFSET 0x07C
55 #define RCGC0_OFFSET 0x100
56 #define RCGC1_OFFSET 0x104
57 #define RCGC2_OFFSET 0x108
58 #define SCGC0_OFFSET 0x110
59 #define SCGC1_OFFSET 0x114
60 #define SCGC2_OFFSET 0x118
61 #define DCGC0_OFFSET 0x120
62 #define DCGC1_OFFSET 0x124
63 #define DCGC2_OFFSET 0x128
64 #define DSLPCLKCFG_OFFSET 0x144
65 #define PIOSCCAL_OFFSET 0x150
66 #define PIOSCSTAT_OFFSET 0x154
67 #define I2SMCLKCFG_OFFSET 0x170
68 #define DC9_OFFSET 0x190
69 #define NVMSTAT_OFFSET 0x1A0
73 #define RCC_USESYSDIV 22
81 #define RCC2_USERCC2 31
82 #define RCC2_DIV400 30
83 #define RCC2_SYSDIV2 23
84 #define RCC2_SYSDIV2LSB 22
85 #define RCC2_USBPWRDN 14
86 #define RCC2_PWRDN2 13
87 #define RCC2_BYPASS2 11
90 #define RIS_MOSCPUPRIS 8
91 #define RIS_USBPLLLRIS 7
105 #define GPIOA_BASE 0x40004000
106 #define GPIOB_BASE 0x40005000
107 #define GPIOC_BASE 0x40006000
108 #define GPIOD_BASE 0x40007000
109 #define GPIOE_BASE 0x40024000
110 #define GPIOF_BASE 0x40025000
111 #define GPIOG_BASE 0x40026000
112 #define GPIOH_BASE 0x40027000
113 #define GPIOJ_BASE 0x4003D000
115 #define GPIO_DATA_OFFSET 0x000
116 #define GPIO_DIR_OFFSET 0x400
117 #define GPIO_IS_OFFSET 0x404
118 #define GPIO_IBE_OFFSET 0x408
119 #define GPIO_IEV_OFFSET 0x40C
120 #define GPIO_IM_OFFSET 0x410
121 #define GPIO_RIS_OFFSET 0x414
122 #define GPIO_MIS_OFFSET 0x418
123 #define GPIO_ICR_OFFSET 0x41C
124 #define GPIO_AFSEL_OFFSET 0x420
125 #define GPIO_DR2R_OFFSET 0x500
126 #define GPIO_DR4R_OFFSET 0x504
127 #define GPIO_DR8R_OFFSET 0x508
128 #define GPIO_ODR_OFFSET 0x50C
129 #define GPIO_PUR_OFFSET 0x510
130 #define GPIO_PDR_OFFSET 0x514
131 #define GPIO_SLR_OFFSET 0x518
132 #define GPIO_DEN_OFFSET 0x51C
133 #define GPIO_LOCK_OFFSET 0x520
134 #define GPIO_CR_OFFSET 0x524
135 #define GPIO_AMSEL_OFFSET 0x528
136 #define GPIO_PCTL_OFFSET 0x52C
137 #define GPIO_PeriphID4_OFFSET 0xFD0
138 #define GPIO_PeriphID5_OFFSET 0xFD4
139 #define GPIO_PeriphID6_OFFSET 0xFD8
140 #define GPIO_PeriphID7_OFFSET 0xFDC
141 #define GPIO_PeriphID0_OFFSET 0xFE0
142 #define GPIO_PeriphID1_OFFSET 0xFE4
143 #define GPIO_PeriphID2_OFFSET 0xFE8
144 #define GPIO_PeriphID3_OFFSET 0xFEC
145 #define GPIO_PCellID0_OFFSET 0xFF0
146 #define GPIO_PCellID1_OFFSET 0xFF4
147 #define GPIO_PCellID2_OFFSET 0xFF8
148 #define GPIO_PCellID3_OFFSET 0xFFC
151 #define ISR_ENABLE_VECTOR 0xE000E100
153 #endif /* HW_REGS_H_ */