X-Git-Url: https://git.cryptolib.org/?a=blobdiff_plain;f=test_src%2Fhw_regs.h;h=c6d859b421fd2da592af69b946c4644880735ca9;hb=8fa939d627fb6230610a38e6468cbc55d006216d;hp=71fb1f660a31ef74eff2d98d5e7d0b4244e7a435;hpb=4f19c43af8afeb3c569eb7b4aa15907832cf8e5c;p=arm-crypto-lib.git

diff --git a/test_src/hw_regs.h b/test_src/hw_regs.h
index 71fb1f6..c6d859b 100644
--- a/test_src/hw_regs.h
+++ b/test_src/hw_regs.h
@@ -1,6 +1,6 @@
 /* hw_regs.h */
 /*
-    This file is part of the ARM-Crypto-Lib.
+    This file is part of the AVR-Crypto-Lib.
     Copyright (C) 2010 Daniel Otte (daniel.otte@rub.de)
 
     This program is free software: you can redistribute it and/or modify
@@ -25,7 +25,9 @@
 #define SET_REG(r,v) (*((volatile uint32_t*)(r))) = (v)
 #define GET_REG(r)   (*((volatile uint32_t*)(r)))
 #define HW_REG(r)    (*((volatile uint32_t*)(r)))
-#define _BV(x)       (1<<(x))
+#define HW16_REG(r)  (*((volatile uint16_t*)(r)))
+#define HW8_REG(r)   (*((volatile uint8_t*)(r)))
+#define _BV(x)       (1UL<<(x))
 
 #define SYSCTL_BASE 0x400FE000
 #define DID0_OFFSET           0x000
@@ -87,6 +89,48 @@
 #define RCC2_BYPASS2     11
 #define RCC2_OSCSR2       4
 
+#define RCGC0_WDT0        3
+#define RCGC0_HIB         6
+#define RCGC0_MAXADC0SPD  8
+#define RCGC0_MAXADC1SPD 10
+#define RCGC0_ADC0       16
+#define RCGC0_ADC1       17
+#define RCGC0_CAN0       24
+#define RCGC0_CAN1       25
+#define RCGC0_WDT1       28
+
+#define RCGC1_UART0       0
+#define RCGC1_UART1       1
+#define RCGC1_UART2       2
+#define RCGC1_SSI0        4
+#define RCGC1_SSI1        5
+#define RCGC1_I2C0       12
+#define RCGC1_I2C1       14
+#define RCGC1_TIMER0     16
+#define RCGC1_TIMER1     17
+#define RCGC1_TIMER2     18
+#define RCGC1_TIMER3     19
+#define RCGC1_COMP0      24
+#define RCGC1_COMP1      25
+#define RCGC1_COMP2      26
+#define RCGC1_I2S0       28
+#define RCGC1_EPI0       30
+
+#define RCGC2_GPIOA       0
+#define RCGC2_GPIOB       1
+#define RCGC2_GPIOC       2
+#define RCGC2_GPIOD       3
+#define RCGC2_GPIOE       4
+#define RCGC2_GPIOF       5
+#define RCGC2_GPIOG       6
+#define RCGC2_GPIOH       7
+#define RCGC2_GPIOJ       8
+#define RCGC2_UDMA       13
+#define RCGC2_USB0       16
+#define RCGC2_EMAC0      28
+#define RCGC2_EPHY0      30
+
+
 #define RIS_MOSCPUPRIS   8
 #define RIS_USBPLLLRIS   7
 #define RIS_PLLLRIS      6